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Active Up-Level Receiver Clamp

IP.com Disclosure Number: IPCOM000041836D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Gaudenzi, GJ: AUTHOR [+2]

Abstract

Fig. 1 depicts a net including a driver circuit and a receiver circuit interconnected by an unterminated length of transmission line. When the driver sends a signal to the receiver circuit (high input impedance), voltage. To optimize net delay switching time and improve net wirability, it is desirable to minimize the reflected voltage on the net and restore the net to a DC value < _ MPUL (Most Positive Up Level). The receiver circuit shown in Fig. 2 contains a clamp circuit that is designed to respond to positive-going transients and limit the net voltage to < MPUL, which is 2.2 volts for the design considered. Transistors T1, T2, TR, diode DR and resistors R1, R2, RC and RS comprise the receiver circuit and transistor TC and resistor RBC comprise the active transient clamp.

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Active Up-Level Receiver Clamp

Fig. 1 depicts a net including a driver circuit and a receiver circuit interconnected by an unterminated length of transmission line. When the driver sends a signal to the receiver circuit (high input impedance), voltage. To optimize net delay switching time and improve net wirability, it is desirable to minimize the reflected voltage on the net and restore the net to a DC value < _ MPUL (Most Positive Up Level). The receiver circuit shown in Fig. 2 contains a clamp circuit that is designed to respond to positive-going transients and limit the net voltage to < MPUL, which is 2.2 volts for the design considered. Transistors T1, T2, TR, diode DR and resistors R1, R2, RC and RS comprise the receiver circuit and transistor TC and resistor RBC comprise the active transient clamp. Circuit operation is as follows: Consider the case when input A is down, transistor T1 is off and output A is up such that TC is on and operating in the inverted mode. Current will flow out of the collector of TC and is determined by the following: I = -(bI+1) X IRBC for Vin = .6 V, RC = RBC = 8.0K and bI = 5, and I = -.675 ma To minimize the clamp DC current flow when the receiver input is at a down level, the TC emitter voltage supply (1.7 V) can be replaced by two diodes as shown in Fig. 3. In this configuration, TC operates in the saturated inverted mode however due to the high reverse impedance of the two diodes, the collector current is minimized to: I = -...