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Memory Circuit Using Lateral PNP Transistors

IP.com Disclosure Number: IPCOM000041837D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Askin, HO: AUTHOR [+2]

Abstract

A silicon-controlled rectifier (SCR) type of latch is formed using lateral PNP transistors which can be made without additional processing steps in certain NPN fabrication methods. Transistors T2 and T3, with resistors R2 and R3, form the actual memory device. Assume EM is low, as is normally the case. If the collector of T3 is initially low, current flows through R3, creating a voltage drop sufficient to turn transistor T2 on. This pulls the base of transistor T3 high, forcing it to turn on, thus keeping its collector low, as assumed. If, on the other hand, the collector of T3 is initially high, little current will flow through R3 so insufficient voltage will be dropped to turn transistor T2 on. Resistor R2 then pulls the base of transistor T3 low, forcing transistor T3 to turn off.

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Memory Circuit Using Lateral PNP Transistors

A silicon-controlled rectifier (SCR) type of latch is formed using lateral PNP transistors which can be made without additional processing steps in certain NPN fabrication methods. Transistors T2 and T3, with resistors R2 and R3, form the actual memory device. Assume EM is low, as is normally the case. If the collector of T3 is initially low, current flows through R3, creating a voltage drop sufficient to turn transistor T2 on. This pulls the base of transistor T3 high, forcing it to turn on, thus keeping its collector low, as assumed. If, on the other hand, the collector of T3 is initially high, little current will flow through R3 so insufficient voltage will be dropped to turn transistor T2 on. Resistor R2 then pulls the base of transistor T3 low, forcing transistor T3 to turn off. Its collector is then pulled high by R3 and R4. Resistor R4 serves to limit the current drawn from the power supply. Transistor T1 acts to gate data onto the cell. Consider the following timing diagrams. Note that EM is a read/write selector, while EP and ERD are cell selectors. If the data input is high when EP goes low and EM goes high (time (1)), transistor T1 will conduct, raising the base voltage of T3. Since T3 can't conduct as its emitter voltage has been raised by EM, nothing happens. EM raises the emitter voltage of T3 to assure that the device is not conducting. When EM is lowered again, at time (2), T3 will then start conducting...