Browse Prior Art Database

Metallized Ceramic and Multi-Level Hybrid Fan-Out Technique

IP.com Disclosure Number: IPCOM000041840D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Kraus, JC: AUTHOR [+3]

Abstract

Fan-out from a substrate-mounted LSI chip is achieved using only two simple buried fan-out layers and a relatively simple top surface fan-out pattern. Only a few layers of a multilayer ceramic (MLC) substrate are used to accomplish a limited amount of chip fan-out so that the remaining chip fan-out lines occupy only two wiring spaces between adjacent chip connections on the top surface of the ceramic substrate. Fig. 1 shows a layout of one quadrant of a typical chip footprint. The twelve lines shown that use buried layers (two layers are required) make it possible to fan-out the remaining lines with a maximum of two lines between chip connection pad locations. It is important to note that two lines never have to pass between two vias that are in adjacent positions since power vias occupy every other position in the substrate.

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Metallized Ceramic and Multi-Level Hybrid Fan-Out Technique

Fan-out from a substrate-mounted LSI chip is achieved using only two simple buried fan-out layers and a relatively simple top surface fan-out pattern. Only a few layers of a multilayer ceramic (MLC) substrate are used to accomplish a limited amount of chip fan-out so that the remaining chip fan-out lines occupy only two wiring spaces between adjacent chip connections on the top surface of the ceramic substrate. Fig. 1 shows a layout of one quadrant of a typical chip footprint. The twelve lines shown that use buried layers (two layers are required) make it possible to fan-out the remaining lines with a maximum of two lines between chip connection pad locations. It is important to note that two lines never have to pass between two vias that are in adjacent positions since power vias occupy every other position in the substrate. In this case then, the two lines can be located as close as process tolerances allow, to the signal connection pads on the substrate. As shown in Fig. 2, when the exposure mask is positioned over the center of the chip site, there is no danger of shorting to a via which is out of position due to distortion. Measurements on substrates indicate that the worst via position uncertainty is 2 mils at the corners of the chip site. By referring to Fig. 2, it can readily be seen that this degree of distortion would not be a problem.

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