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Incremental Model Development for Timing Analysis

IP.com Disclosure Number: IPCOM000041848D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 65K

Publishing Venue

IBM

Related People

Auch, AG: AUTHOR [+2]

Abstract

Timing Analysis [*] requires the development of an entire model of a hardware system at every level of Engineering Change (EC) and the re-evaluation of the entire system's logic path delays. The method illustrated in the figures, creates a model which includes only the logic and paths affected by the EC and required by a Timing Analysis program. The method minimizes a path delay tracing run and the volume of output data that the designer must evaluate. Further, the data that is provided is only that data which is significant to the changes which were made in the design. There are two basic algorithms in the Incremental Timing Analysis (ITA) process.

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Incremental Model Development for Timing Analysis

Timing Analysis [*] requires the development of an entire model of a hardware system at every level of Engineering Change (EC) and the re-evaluation of the entire system's logic path delays. The method illustrated in the figures, creates a model which includes only the logic and paths affected by the EC and required by a Timing Analysis program. The method minimizes a path delay tracing run and the volume of output data that the designer must evaluate. Further, the data that is provided is only that data which is significant to the changes which were made in the design. There are two basic algorithms in the Incremental Timing Analysis (ITA) process. In Phase I, given the circuits or nets in the design which have been modified as a result of an EC, the object is to determine the logic impacted by the change along with the required clock and Timing Analysis (TA) flagged logic. The clock and TA flagged logic are necessary for a TA Trace Program to perform timing tests on the delay paths at latches and arrays. In Phase II, the objective of the algorithm is to automatically determine the blocks or nets which have been modified as a result of an EC and provide them to the Phase I process. An example of an incremental model is shown in Fig. 1. Assume that the output net of Block 1 is changed to include a new interconnection to Block 7. The x at the output of Block 1 indicates a change. A forward trace from Block 1 includes Blocks, 2, 3, 4, 5, 6, 7, 8 and the shift register latches (SRLs) at which the paths end. A backward trace from Block 1 includes Block 9, all the other Blocks in the path from the top input to Block 9, and the latches at which these paths end. The incremental logic which requires analysis as a result of the change is shown in the diagram between the dashed lines. It is not necessary to evaluate the rest of the model since it is not affected by the change. It is not necessary to be concerned about lines feeding into the incremental model (such as the line from Block 10 to Block 2) since the path delays and timing along these paths were not changed and, therefore, are ignored in the tracing process. If a delay change does occur on one of these lines, for example, the path would be included in an incremental trace of the point causing the change. Many changes can be merged to form one incremental model. The appropriate clock lines to SRLs and Arrays are also included in the incremental model. These are required for TA to perform the necessary tests. Fig. 2 shows the ITA methodology. The ITA Phase I program 10 is called Partitioning and it interfaces with a program 11, called GENCUT. The input to the Partitioning program is a set of EC Specifications 12 and the logic 13 which has been modified. Partitioning derives the incremental logic 14 affected by the EC and passes it to progra...