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Browse Prior Art Database

On-Chip Multiplexer Oriented System for Josephson Testing

IP.com Disclosure Number: IPCOM000041856D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 4 page(s) / 45K

Publishing Venue

IBM

Related People

Bucelot, TJ: AUTHOR [+2]

Abstract

MOST (Multiplexer Oriented System for Testing) is a comprehensive test scheme for making circuit nodes highly visible to tester equipment. Its implementation does not suffer the penalty of large amounts of chip area and/or I/O being dedicated solely to testing. By taking advantage of the latching nature of Josephson logic and its high serial fanout capabilities, nodes to be monitored can be multiplexed into the existing shift register latch string so that their data can be serially shifted to the tester equipment. This system-oriented scheme is available for testing and diagnostic purposes at chip, module and machine levels.

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On-Chip Multiplexer Oriented System for Josephson Testing

MOST (Multiplexer Oriented System for Testing) is a comprehensive test scheme for making circuit nodes highly visible to tester equipment. Its implementation does not suffer the penalty of large amounts of chip area and/or I/O being dedicated solely to testing. By taking advantage of the latching nature of Josephson logic and its high serial fanout capabilities, nodes to be monitored can be multiplexed into the existing shift register latch string so that their data can be serially shifted to the tester equipment. This system-oriented scheme is available for testing and diagnostic purposes at chip, module and machine levels. Because all chip primary inputs and primary outputs can be monitored in MOST, it provides the capability of isolating faults to individual chips or interchip wiring during module and system testing without removing the chip from the module or the module from the system. No extra latches need be added to a chip and, hence, potentially severe chip yield and machine cycle time penalties are not incurred. Description MOST uses existing shift register latches (SRLs) to monitor critical nodes. A critical node is any primary input (PI) not going directly to an SRL, or any primary output (PO) not coming directly from an SRL, or any internal node whose monitored condition would significantly aid diagnosability. To illustrate, Fig. 1 shows a chip that is to be tested without incorporating MOST. The combinatorial networks are designated CNl, ... CN3, while the 1-bit shift register latches are designated SRL. Although the PIs and POs are accessible for testing, several of the internal nodes are inaccessible which would render faults difficult to diagnose to the gate level. In principle, SRLs could be added to capture critical nodes and therefore make the chip diagnosable, but the cost of SRLs, in terms of device count (chip area) and complexity (device reliability), makes their liberal addition prohibitive. In contrast to adding more SRLs, MOST makes more efficient use of those already present. Monitoring of Primary Inputs Control lines, originating from PIs, may be monitored by simply extending them to multiplexers (mux) that serve as inputs to the existing SRLs. On a test cycle, the mux inputs would be gated into the SRL so that they could be shifted out for inspection. Because the serial fanout of Josephson logic is virtually unlimited and the input control line passes over its logic devices before the monitoring mux, the extension of the control line causes no time delay to the logic. In this way all PIs can be monitored to verify the inputs to chips at chip, module and system levels. Fig. 2 shows a chip to be tested with MOST implemented. (PIs with Long Line Receivers are discussed below.) Internal critical nodes and POs may be extended in the same way, provided that the extensions do not add significant delay to the critical path (see below). Monitoring of In...