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Direct Coupled Self-Gating and

IP.com Disclosure Number: IPCOM000041857D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Gheewala, TR: AUTHOR [+2]

Abstract

This article relates generally to Direct Coupled Logic (DCL) circuits and more specifically to a self-gating AND (SGA) circuit which utilizes DCL devices and has improved density over known Current Injection Logic (CIL) SGA circuits. DCL circuits have been proposed * which have high density, better punchthrough characteristics and higher immunity to trapped flux than their corresponding CIL counterparts. Referring now to the figure, a DCL SGA (circuit 1) is shown. In the figure, device Q1 is a "low LI0", three-junction interferometer. Q2 is a Josephson junction device which is utilized as a reference junction in circuit 1. Devices Q1, Q2 are cross-coupled to DCL circuits Q4, Q3, respectively. Circuits Q4, Q3 are DCL OR gates similar to those described in [*].

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Direct Coupled Self-Gating and

This article relates generally to Direct Coupled Logic (DCL) circuits and more specifically to a self-gating AND (SGA) circuit which utilizes DCL devices and has improved density over known Current Injection Logic (CIL) SGA circuits. DCL circuits have been proposed * which have high density, better punchthrough characteristics and higher immunity to trapped flux than their corresponding CIL counterparts. Referring now to the figure, a DCL SGA (circuit 1) is shown. In the figure, device Q1 is a "low LI0", three-junction interferometer. Q2 is a Josephson junction device which is utilized as a reference junction in circuit 1. Devices Q1, Q2 are cross-coupled to DCL circuits Q4, Q3, respectively. Circuits Q4, Q3 are DCL OR gates similar to those described in [*]. A latch storage loop 2 is electrically coupled to device Q1, which is the sensing device for SGA circuit 1. The inductance of loop 2 is provided by two turns of control line portion 3 over device Q1. Outputs C,T, which have a parallel fan of two, are connected to circuits Q3, Q4, respectively. If a "0" is intially stored in latch storage loop 2, Q1 never switches and there is no output at T (true). As the gate current increases, Q2 switches, and both inputs to Q3 are available. Circuit Q3 switches providing an output at C (complement). The design constraints therefore are: 1) Q1 should switch before Q2 when a "1" is stored in loop 2, and (2) If a "0" is stored, Q2 should switch...