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Transistor Process Enhancement

IP.com Disclosure Number: IPCOM000041861D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Dockerty, RC: AUTHOR

Abstract

An enhanced bipolar transistor process technique is described here to make LPNP transistors with sub-micron base widths. The base width is not dependent on photolithographic image definition. Polysilicon contacts are made to the emitter and collector of the LPNP device. The process also makes sub-micron width polysilicon resistors. The resistor width is not set by photolithography. Process 1. Standard process to fabricate the structure of Fig. 1, where NI, II, etc., indicates silicon nitride layer I, II, etc. and PI, PII indicates polysilicon layer I, II, etc. Oxidize PII sidewall - grow 1 m oxide (see Fig. 1). 2. Etch NII in hot phosphoric acid or CF4 3. Etch PII. 4. RIE (reactive ion etch) NI (the sidewall oxide is the etch mask). 5. Wet etch the sidewall oxide. 6. Oxidize the exposed PI - grow 500 ˜ SiO2 (OIII). 7.

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Transistor Process Enhancement

An enhanced bipolar transistor process technique is described here to make LPNP transistors with sub-micron base widths. The base width is not dependent on photolithographic image definition. Polysilicon contacts are made to the emitter and collector of the LPNP device. The process also makes sub-micron width polysilicon resistors. The resistor width is not set by photolithography. Process 1. Standard process to fabricate the structure of Fig. 1, where NI, II, etc., indicates silicon nitride layer I, II, etc. and PI, PII indicates polysilicon layer I, II, etc. Oxidize PII sidewall - grow 1 m oxide (see Fig. 1). 2. Etch NII in hot phosphoric acid or CF4 3. Etch PII. 4. RIE (reactive ion etch) NI (the sidewall oxide is the etch mask). 5. Wet etch the sidewall oxide. 6. Oxidize the exposed PI - grow 500 ~ SiO2 (OIII). 7. Extrinsic base implant - boron, NI masks the implant (see Fig. 2). 8. PR (photo resist) (resist covers NI #3 of Fig. 2). 9. Etch exposed NI and strip resist. 10. RIE poly I (EEPD (Etch End-Point Detector) + 5%)), NI and OIII are the etch masks. 11. Base poly PR (see Fig. 3). 12. RIE oxide in CF4 (EEPD + 100%). 13. RIE base poly (EEPD + 100% SF6/Cl2). 14. Etch NI in DE100 (see Fig. 4). 15. Poly resistor implant (base poly PR protects base of LPNP). 16. Strip PR. 17. Reox 500 . ~ 18. Oxide overcoat. 19. Nitride overcoat.
20. Continue process (see Fig. 5). Basewidth and resistor width are determined by the oxide thickness...