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'Rail Go Away' Process for Polysilicon Emitter Transistor

IP.com Disclosure Number: IPCOM000041864D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Chu, SF: AUTHOR [+3]

Abstract

Reactive ion etching (RIE) is used to define the polysilicon emitter in certain bipolar integrated circuits. Rails are left behind at the bottom of the steps due to the directional RIE process. These steps are the result of a previous RIE process. The presence of these rails will cause leakage in the transistor, and shorts in the resistor and between metal lines after the metallization process. Isotropic etching, such as plasma etching or pyrocatechol wet etching, has been considered. These methods do not leave rails. However, these etching processes cause an undercut which affects the emitter dimension. In addition, the etch rate ratio between the polysilicon and silicon nitride is small in the case of plasma etching. As a result, a missing silicon nitride layer can occur above the base and collector areas.

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'Rail Go Away' Process for Polysilicon Emitter Transistor

Reactive ion etching (RIE) is used to define the polysilicon emitter in certain bipolar integrated circuits. Rails are left behind at the bottom of the steps due to the directional RIE process. These steps are the result of a previous RIE process. The presence of these rails will cause leakage in the transistor, and shorts in the resistor and between metal lines after the metallization process. Isotropic etching, such as plasma etching or pyrocatechol wet etching, has been considered. These methods do not leave rails. However, these etching processes cause an undercut which affects the emitter dimension. In addition, the etch rate ratio between the polysilicon and silicon nitride is small in the case of plasma etching. As a result, a missing silicon nitride layer can occur above the base and collector areas. The improved process to otherwise overcome rails is as follows: 1. The conventional bipolar process is followed up to emitter polysilicon deposition. The structure at this point includes recessed oxide isolation (ROI) isolating the base-emitter region 9 from other such regions and collector reach-through region 10. Over the surface of this structure are chemical vapor deposited (CVD) silicon dioxide layer 11, P doped polysilicon layer 12, silicon dioxide layer 13 and silicon nitride layer 14, as seen in Fig. 1. A layer 15 of intrinsic polysilicon is put down on the wafer by chemical vapor deposition. The N doping in layer 15 is accomplished by arsenic ion implant. Let us call the thickness of this polysilicon Tp . 2. A layer 16 of silicon dioxide is deposited on top of the polysilicon layer 15. The thickness of this oxide is called T1 . 3. Photolithography is used to define the emitter resulting in resist mask 17. Fig. 1 shows the transistor structure at this point of the process. The emitter area and the potential rail area are identified. These two areas are shown again in Fig. 2. In Figs. 2 to 8, only these two areas are compared with the emitter area on the left and the potential rail area on the right. In this example a vertical step is depicted. This is the worst-case topology. 4. The exposed oxide area 16 is removed by RIE in CF4 or CHF3 to end point plus 20% over...