Browse Prior Art Database

NMOS Function Generator

IP.com Disclosure Number: IPCOM000041865D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Lo, TC: AUTHOR

Abstract

An NMOS Function Generator disclosed here has two control signals: X and Y. This circuit can be inserted into any data path to perform the following logic: Fig. 1 shows the circuit implementation using Differential Cascode Voltage Switch Scheme. Fig. 2 shows a single-ended alternative. In both Fig. 1 and Fig. 2, X and Y are control signals, I is the input line, and Q is the output line. The NMOS transistor 10 in Fig. 1 is a depletion-mode device and has a ratioed load. The NMOS transistors 12, 14 in Fig. 1 and transistors 16, 18 in Fig. 2 have ratioed loads.

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NMOS Function Generator

An NMOS Function Generator disclosed here has two control signals: X and Y. This circuit can be inserted into any data path to perform the following logic: Fig. 1 shows the circuit implementation using Differential Cascode Voltage Switch Scheme. Fig. 2 shows a single-ended alternative. In both Fig. 1 and Fig. 2, X and Y are control signals, I is the input line, and Q is the output line. The NMOS transistor 10 in Fig. 1 is a depletion-mode device and has a ratioed load. The NMOS transistors 12, 14 in Fig. 1 and transistors 16, 18 in Fig. 2 have ratioed loads.

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