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CPU and Support Processor Communication Mechanism

IP.com Disclosure Number: IPCOM000041884D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Campbell, RA: AUTHOR [+4]

Abstract

In a data processing system that includes a primary CPU and a support processor, various communications between the primary CPU and support processor are needed for functions such as diagnose instruction and display storage data, etc. A low cost and simple mechanism employing an 8-byte register is used to transfer commands and data between the processors. The 8-byte register can be sourced or destined via decodes in the BRANCH microword on the primary CPU and can be scanned by the support processor without stopping the primary CPU clocks. Along with the 8-byte register, interrupts and response latches are provided on both processors for handshaking. They insure that the register is not being scanned when the CPU is trying to reference it.

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CPU and Support Processor Communication Mechanism

In a data processing system that includes a primary CPU and a support processor, various communications between the primary CPU and support processor are needed for functions such as diagnose instruction and display storage data, etc. A low cost and simple mechanism employing an 8-byte register is used to transfer commands and data between the processors. The 8- byte register can be sourced or destined via decodes in the BRANCH microword on the primary CPU and can be scanned by the support processor without stopping the primary CPU clocks. Along with the 8-byte register, interrupts and response latches are provided on both processors for handshaking. They insure that the register is not being scanned when the CPU is trying to reference it. In addition, support processor commands to raise an interrupt and to set response latches do not require stopping of the CPU clocks. With this attribute, the 8-byte register communications are used both when CPU is in the soft-stop state or operating state. During the execution of an operation involving the CPU and support processor, initial interrupt, data transfer and ending sequence can occur. To initiate a communication operation, an interrupt is sent to the other processor. This interrupt is responded to by setting a response latch on the other processor. The data transfer includes an 8-byte command transfer and subsequent data transfers, if needed. The ending sequence invo...