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Microprocessor Stack Address Transfer Bus

IP.com Disclosure Number: IPCOM000041896D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Cannon, JW: AUTHOR [+2]

Abstract

A logic multi-function bus mechanism is described that is particularly useful in microprocessor designs. The circuitry has an efficient design to enable transfer of stack addresses from two possible sources to the appropriate stack address register. The units necessary to accomplish the transfers are depicted in the drawing. The dotted lines depict logic module boundaries. The stack address is normally specified by certain bits in the microcode control word supplied from a read only storage (ROS). In this example one byte or eight bits are assumed. The eight bits are loaded into a destination register 1 and are then driven through drivers 7 to the Multi-function Interface Bus (MIB) 2, which is a common bus interfacing to most of the logic function modules comprising the microprocessor system.

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Microprocessor Stack Address Transfer Bus

A logic multi-function bus mechanism is described that is particularly useful in microprocessor designs. The circuitry has an efficient design to enable transfer of stack addresses from two possible sources to the appropriate stack address register. The units necessary to accomplish the transfers are depicted in the drawing. The dotted lines depict logic module boundaries. The stack address is normally specified by certain bits in the microcode control word supplied from a read only storage (ROS). In this example one byte or eight bits are assumed. The eight bits are loaded into a destination register 1 and are then driven through drivers 7 to the Multi-function Interface Bus (MIB) 2, which is a common bus interfacing to most of the logic function modules comprising the microprocessor system. The MIB is designed to accommodate a variety of functions of which the loading of stack address registers is only one. One of the two different stack address registers 3,4 can be specified to receive the data. Since control bits from ROS are fixed and cannot be modified, a problem can occur during power-up microdiagnostics when it is desirable to check out each stack location. This means that each stack address must be represented by a unique word in ROS. If 256 locations are to be checked out, then at least 256 unique words in ROS must be set aside for this purpose. A microcode Do-Loop could alternatively accomplish this task if a means of modifying the address and presenting the modified address to a stack address register could be accomplished. The Processor Bus, which is driven from the microprocessor's arithmetic logic unit (ALU), can provide a means of generating sequential bytes of data within a Do- Loop. If a means can be implemented to efficiently present the processor bus to the stack address registers without consuming a substantial number of pins, then it would be possible to implement a microcode Do-Loop that g...