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Browse Prior Art Database

Direct Memory Access Controller

IP.com Disclosure Number: IPCOM000041897D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 4 page(s) / 63K

Publishing Venue

IBM

Related People

Edick, SE: AUTHOR

Abstract

A direct memory access controller (DMAC) is provided with programmable address/data bus size by placing a function, which is normally handled by software in two communicating processors, or in multiple hardware components, into a single piece of hardware and making it programmable for different processors. The DMAC has the ability to interface two bus structures which differ in their bus sizes. The user of the DMAC has the option to program the number of input/output (I/O) terminals of the DMAC dedicated to the address and data bus of the system into which it is plugged or connected. An example of this option is using the DMAC to transfer data from a memory which has a word size of 8 bits to a memory which has a word size of 16 bits.

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Direct Memory Access Controller

A direct memory access controller (DMAC) is provided with programmable address/data bus size by placing a function, which is normally handled by software in two communicating processors, or in multiple hardware components, into a single piece of hardware and making it programmable for different processors. The DMAC has the ability to interface two bus structures which differ in their bus sizes. The user of the DMAC has the option to program the number of input/output (I/O) terminals of the DMAC dedicated to the address and data bus of the system into which it is plugged or connected. An example of this option is using the DMAC to transfer data from a memory which has a word size of 8 bits to a memory which has a word size of 16 bits. The same DMAC is then used to transfer data from a memory with a word size of 32 bits to a memory with a word size of 16 bits. This option also allows a user to interface two microprocessor systems with buses which differ in size and are not necessarily compatible in their clock rates. A block diagram of the DMAC is shown in Fig. 1, where n=1 or 2 or 4. The functions available in the DMAC include address registers, clock, bidirectional buffers, read/write control, interrupt request circuits with programmable timer, DMA request/acknowledge circuits, word size select and priority request select. The word size select may be as follows:

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Additional features may include a +5-volt supply voltage, tri-state bus, programmable to minimize pin count, and multiplexed data and address bus. The controller, which is TTL compatible, allows the user to transfer data between two systems with different word sizes provided that the instruction set is compatible for both systems. A more detailed block diagram of the DMAC is shown in Fig. 2, with a read/write control logic block diagram shown in Fig. 3. The DMAC operates as follows: I. Initialization of data transfer 1. DMA request from microprocessor or system A to DMAC 2. DMA acknowledge from DMAC to microprocessor A 3. Microprocessor A sends the following information to DMAC: a. sending address word size (8, 16 or 32) b. sending data word size (8, 16 or
32) c. time required to do DMAC d. DMA clock control instruction (4 options): (1) use microprocessor or system A clock to transfer data
(2) use microprocessor or system B clock to transfer data (3) use microprocessor or system A clock to transfer data from memory of system A into DMAC temporary data register, then system B clock to transfer data from DMAC temporary data register into system B memory. (4) control data flow with DMAC clock e. address block size to be transferred f. the starting address of where data is to be retrieved 4. DMAC sends DMA request to system B 5. System B acknowledges request from DMAC 6. System B sends the following information to DMAC: a. receiving address word size (8, 16, 32) b. receiving data word size (8, 16, 32) c. starting receiving addres...