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Microprocessor Load Stack Address Control Command

IP.com Disclosure Number: IPCOM000041898D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Cannon, JW: AUTHOR [+2]

Abstract

A logic function bus mechanism is described that is particularly useful in microprocessor designs. The circuitry is intended to transfer control function information between logic modules and to develop a stack address from multiple sources of information and transfer that address to a stack address register. A second level block diagram of the major components of this mechanism is illustrated in the drawing. Logic module boundaries are indicated by the dotted line. A multifunction interface bus (MIB) 1 is used as a common bus interfacing between various logic modules. A control command is implemented to use the destination field from the microsystem's read-only storage (ROS), which contains the storage media for the system's microcode.

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Microprocessor Load Stack Address Control Command

A logic function bus mechanism is described that is particularly useful in microprocessor designs. The circuitry is intended to transfer control function information between logic modules and to develop a stack address from multiple sources of information and transfer that address to a stack address register. A second level block diagram of the major components of this mechanism is illustrated in the drawing. Logic module boundaries are indicated by the dotted line. A multifunction interface bus (MIB) 1 is used as a common bus interfacing between various logic modules. A control command is implemented to use the destination field from the microsystem's read-only storage (ROS), which contains the storage media for the system's microcode. This destination field is assumed to be 8 bits wide and is loaded into a destination register 2. Destination register 2 drives the MIB. Control commands are implemented which use the destination field to decode a variety of actions to be taken within the processor. These actions are grouped into one instruction because they are either too specialized or too minor to demand a unique microcode instruction. The MIB is used to transmit the destination field to those modules involved in the decode and corresponding activities. Some examples of the types of functions that would normally be involved in this type activity are: Load Stop-On-Address Comparator, Load various keys into an Address Key Register, Initiate a Segmentation Register Transfer, Reset Timer Interrupt, Load Op-Code, Load Console Information, Load Interrupt Masks, etc. These functions can all be easily encoded into the destination field in some convenient manner. One of these control functions utilizes the MIB in a unique manner. This function is called Load Stack Address (LSA). It is invoked by specifying a control function with bit 3 "OFF" in the destination field. All other bits must be "ON" for an LSA function, but only bit 3 is checked when decoding an LSA. All functions other than an LSA must have bit 3 "ON". An LSA function must occur each time that the processor fetches an instruction, such as an IBM Series/1 processor instruction, from main storage. Most of these instructions involve working with General Registers which are located in Local Store. Two possible Stack Address Registers are allowed under Series/1 architecture; each register pointing to one of eight possible locations. A microcode control instruction with LSA specified is executed after the Series/1 instruction is fetched to set each Stack Address Register to the location of the General Registers indicated by the Series/1 instruction. Bits 5 through 7 of the Series/1 instruction designate 1 of 8 possible registers referred to as Stack Register 1 (SR1). Stack...