Browse Prior Art Database

True/Complement Generator

IP.com Disclosure Number: IPCOM000041901D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Coelho, F: AUTHOR [+2]

Abstract

The true/complement generator shown in the drawing is to be used for providing the true and complement values 0 and 0/-/, respectively, of input address bits, to an address decoder for selecting word lines of a memory. These signals are sequenced to prevent undesired selections of word lines due to the simultaneous up levels of 0 and 0/-/ during their transient periods. The generator comprises two identical circuits 1 and 2 providing signals 0/-/ and 0, respectively, from the signal on input IN. The input signal is applied to circuit 2 through an inverting stage. Circuit 1 has a feedback path comprising of resistor bridges R2, R1 and R4, R3 which are connected to the 0 output in circuit 2. Circuit 2 has the same resistor bridge arrangement connected to output 0/-/ of circuit 1.

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True/Complement Generator

The true/complement generator shown in the drawing is to be used for providing the true and complement values 0 and 0/-/, respectively, of input address bits, to an address decoder for selecting word lines of a memory. These signals are sequenced to prevent undesired selections of word lines due to the simultaneous up levels of 0 and 0/-/ during their transient periods. The generator comprises two identical circuits 1 and 2 providing signals 0/-/ and 0, respectively, from the signal on input IN. The input signal is applied to circuit 2 through an inverting stage. Circuit 1 has a feedback path comprising of resistor bridges R2, R1 and R4, R3 which are connected to the 0 output in circuit 2. Circuit 2 has the same resistor bridge arrangement connected to output 0/-/ of circuit 1. In circuit 1, the input signal is applied to transistors T1 and T4 which, in conjunction with transistor T3, control the level on output 0/-/ when input signal IN is at its down and up levels. The feedback from output 0 is applied to the base of transistors T2 and T5 which control the level on output 0/-/ during the transient switching period of the input signal. As long as output 0 is at a level higher than a threshold V(T), it maintains transistors T2 and T5 ON. Transistor T2 being ON, transistor T3 is OFF and transistor T5 acts like transistor T4 during the steady state period when the IN signal is at an up level. Thus, switching from the down level to the up l...