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Browse Prior Art Database

Picocode Addressing Ros/Ram Organization

IP.com Disclosure Number: IPCOM000041904D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Pauporte, A: AUTHOR [+3]

Abstract

This article relates to the implementation of the machine control picocode in such a way that it can be modified without significant impact on the machine cost and performance. In the machines controlled by picocode, the picocode is generally implemented in a read only storage (ROS). However, for fast machines having a short basic cycle, high speed ROS units are required. These high speed ROS units are not programmable, and consequently the picocode cannot be modified. The picocode cannot be implemented in a random-access memory (RAM) since high speed and high density RAM will be required, which has a significant impact on the machine cost.

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Picocode Addressing Ros/Ram Organization

This article relates to the implementation of the machine control picocode in such a way that it can be modified without significant impact on the machine cost and performance. In the machines controlled by picocode, the picocode is generally implemented in a read only storage (ROS). However, for fast machines having a short basic cycle, high speed ROS units are required. These high speed ROS units are not programmable, and consequently the picocode cannot be modified. The picocode cannot be implemented in a random-access memory (RAM) since high speed and high density RAM will be required, which has a significant impact on the machine cost. The proposed solution consists in performing an indirect addressing using address pointers in a RAM, which makes the picocode modifiable, the picocode being a ROS in order to decrease the RAM size to the minimum, and maintaining part of the picocode in the RAM and part of the picocode in the ROS. The picocode address generation mechanism works without knowing if the picocode is in the ROS or in the RAM. A single address space is presented by both memories. The picocode RAM/ROS partitioning is made as follows: A. Picocode located in the ROS and directly addressed: It is the straightforward instruction picocode which is strictly modular, which does not use branch or link picoinstructions and which is not interruptible. It is a ROS implementation of hardware logic. The operations controlle...