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Microprocessor Change Address Circuitry for Branch Instructions

IP.com Disclosure Number: IPCOM000041905D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 60K

Publishing Venue

IBM

Related People

Cannon, JW: AUTHOR [+2]

Abstract

A logic function circuit is described that is particularly useful in microprocessor designs. The circuitry is intended to interface to a read-only storage (ROS) and is particularly efficient for implementing conditional branch instructions or more specifically an N-way branch. An N-way branch is a form of conditional branch that checks for a multitude of conditions instead of a simple true/false decision based on a single condition. It is particularly useful in a microprocessor-based system design since the microprocessor must often evaluate multiple bits in a bit stream. For example, the microprocessor is usually required to examine a number of bits in the machine language instruction in order to determine the op-code.

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Microprocessor Change Address Circuitry for Branch Instructions

A logic function circuit is described that is particularly useful in microprocessor designs. The circuitry is intended to interface to a read-only storage (ROS) and is particularly efficient for implementing conditional branch instructions or more specifically an N-way branch. An N-way branch is a form of conditional branch that checks for a multitude of conditions instead of a simple true/false decision based on a single condition. It is particularly useful in a microprocessor-based system design since the microprocessor must often evaluate multiple bits in a bit stream. For example, the microprocessor is usually required to examine a number of bits in the machine language instruction in order to determine the op- code. If the microprocessor is required to individually examine each bit (usually
5) in the op-code field, too much time would be consumed and machine performance would suffer dramatically. An N-way branch allows the op-code to be evaluated and a branch to the proper subroutine to be accomplished all within one microcycle. An N-way branch requires several machine facilities working together in order to be accomplished. The specific register segment must be specified and presented for evaluation. By using a mask, a specific group of bits within that register must be specified and selected for evaluation. After evaluation of the specified bits, the microcode address must be modified accordingly. Since the microcode address generator often resides on a different logic module than the registers requiring evaluation and also on a different logic module than the mask which specifies the bits within that register requiring evaluation, an efficient method of interfacing between these units must be implemented that minimizes the pin count overhead. The implementation described herein accomplishes the above tasks with little or no increase in the pin count by uniquely utilizing an available 8 bit common interface bus which interconnects each logic module involved in the microprocessor design. The microprocessor utilizes a three-phase overlapped ROS as described in U.S. Patent 4,156,925. Each micro-instruction word provides the address of the next sequential instruction for its associated ROS. Twelve bits of address are required to address 4K of ROS. Eight of these bits can be modified by a conditional branch (USE) instruction (Fig. 1). In order to accomplish a savings of approximately 100 logic gates, the microcode assembler is required to assure that any...