Dismiss
The Prior Art Database and Publishing service will be updated on Sunday, February 25th, from 1-3pm ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

# CECL Design Method

IP.com Disclosure Number: IPCOM000041906D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 64K

IBM

## Related People

Massetti, MA: AUTHOR

## Abstract

An improved method is provided for laying out cascode emitter coupled logic (CECL) circuits which decreases turn-around time when compared with custom design or known layouts of CECL circuits. In this method similar logic functions are grouped and a master image is personalized. A typical three level CECL tree is illustrated in Fig. 1. Since CECL circuits can be uniquely identified by the logic function that they perform, the function itself becomes the basis from which the layout is formed. Consequently, similar logic functions yield similar circuit structures. Accordingly, the ability to group the circuits by logic function is the first step towards reducing the time to form a CECL layout. The logic functions are all kept in a single data base for several aspects of the CECL design.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

CECL Design Method

An improved method is provided for laying out cascode emitter coupled logic (CECL) circuits which decreases turn-around time when compared with custom design or known layouts of CECL circuits. In this method similar logic functions are grouped and a master image is personalized. A typical three level CECL tree is illustrated in Fig. 1. Since CECL circuits can be uniquely identified by the logic function that they perform, the function itself becomes the basis from which the layout is formed. Consequently, similar logic functions yield similar circuit structures. Accordingly, the ability to group the circuits by logic function is the first step towards reducing the time to form a CECL layout. The logic functions are all kept in a single data base for several aspects of the CECL design. From this data base a separate routine is used to create circuit node lists, similar to those used in ASTAP, in another data set. The next step is to use a PASCAL routine written for the layout technique. Since differential CECL circuits have both the logical true and complement inputs present for each logic level, circuits are grouped based on differences in input polarities. For example, an AND circuit of two levels can have a true output for one of the combinations 00, 01, 10 or 11, with the only difference between a circuit implementing 00 and one implementing 10 is the polarity of the first input, regardless of the actual levels of the inputs. All that is important is that the relative order of the inputs in either tree remains the same. The output of the PASCAL routine lists the trees according to the groups created. The first tree in each group is considered the reference tree, and the following trees in the group are listed with the inputs that are reversed in polarity from the reference tree. This routine is continued until each tree's node list has been exhaustively checked against all others to form groups, such as the following: Sample of Grouping Results The number of CECL Functions is 11. The number of CECL Groupings is 4. GROUP: 1 Inputs Swapped Logical Function

(Image Omitted)

Both trees have inputs at same polarity. Prior to the existence o...