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Browse Prior Art Database

Inter-Station Clock Synchronization for a Time Division Transmission System

IP.com Disclosure Number: IPCOM000041909D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 62K

Publishing Venue

IBM

Related People

Ambroise, M: AUTHOR [+2]

Abstract

This article describes a clock synchronization method in which a periodic synchronization signal is delivered to the stations of a timedivision transmission system, each of them using it with its local asynchronous clock to regenerate a reference time. Typical time division transmission applications run at 2 Mbps, and each data sample is included in a 488 ns period, called "Data Slot", corresponding to a 2.048 MHz frequency. The clocking system used to control the data slot switching uses a 16.384 MHz clock. Information within a data slot is time referenced. This is done by defining a position for each data slot inside a frame itself identified by a time reference. Let us assume data slots are identified by their time position inside a frame of n = 256 time slots.

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Inter-Station Clock Synchronization for a Time Division Transmission System

This article describes a clock synchronization method in which a periodic synchronization signal is delivered to the stations of a timedivision transmission system, each of them using it with its local asynchronous clock to regenerate a reference time. Typical time division transmission applications run at 2 Mbps, and each data sample is included in a 488 ns period, called "Data Slot", corresponding to a 2.048 MHz frequency. The clocking system used to control the data slot switching uses a 16.384 MHz clock. Information within a data slot is time referenced. This is done by defining a position for each data slot inside a frame itself identified by a time reference. Let us assume data slots are identified by their time position inside a frame of n = 256 time slots. All stations in the system must have the same reference time which is given by a frame synchro (FS) signal delivered every 125 ms (256 x 488 ns) and propagated from station to station. As data slots are propagated on a serial link at a rate of 2 Mbps, each data slot has to be sampled in, then out, wherever it may be on the serial link, during a period of 488 ns. In each station the FS signal represents the reference time. The transmission of one data slot from one station to the other will take one slot time (488 ns). For simplifications there is only one switching stage per station (if more, one slot time per stage must be added). Fig. 1 shows that to keep the same constant time between the FS signal and one given data slot in all stations, the FS signal propagated to the following station will have to be delayed at the same value as the data slot in the sending station (one slot time according to the assumption). 1.Master Station Synchro Generation The local
16.384 MHz clock generates a FS signal every 125 ms to sample the data into the station. It also generates a delayed FS signal every 125 ms according to the data slot switching delay and sends it to the following station. There, the FS signal is controlled by a 2.048 MHz clock derived from the 16.384 MHz local clock. Note that in Fig. 5, since there are 2 switching stages in station 1, the FS signal is sent with the corresponding delay in order to regenerate a local FS delayed by 2 slot times in station 2. 2. Slave Station Synchro Generation Regeneration (solid lines of Fig. 2) When the FS IN signal arrives from the master station, it is sampled by D-latch I on the first 16 MHz local clock r...