Browse Prior Art Database

SDLC Adapter Multiplexer

IP.com Disclosure Number: IPCOM000041911D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Callens, P: AUTHOR

Abstract

This is a system for multiplexing digital information provided by two different sources over a single transmission line on a priority basis. The transmission link represented in the figure, obtaining by juxtaposing figures 1A and 1B, is meant to transmit data out of two terminals attached to adapters at location A to two terminals attached to adapters at location B. Each transmit adapter of location A is made to provide a data bit over a data input D1 or D2 under the control of a clock signal C1 or C2, respectively. At location B the received bits D1 and D2 have to be forwarded to the respectively attached terminals under the control of clock signals C1 and C2 . We will also assume that the data applied to input D1 is coded in the SDLC (synchronous data link control) mode.

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SDLC Adapter Multiplexer

This is a system for multiplexing digital information provided by two different sources over a single transmission line on a priority basis. The transmission link represented in the figure, obtaining by juxtaposing figures 1A and 1B, is meant to transmit data out of two terminals attached to adapters at location A to two terminals attached to adapters at location B. Each transmit adapter of location A is made to provide a data bit over a data input D1 or D2 under the control of a clock signal C1 or C2, respectively. At location B the received bits D1 and D2 have to be forwarded to the respectively attached terminals under the control of clock signals C1 and C2 . We will also assume that the data applied to input D1 is coded in the SDLC (synchronous data link control) mode. The bit streams provided through D2 are first submitted to conventional over-stuffing operation. This means that any time a bit pattern "11111" contained within the shift register SR2 is decoded by DECODER 2, a bit 0 is inserted within the incoming bit stream. The data stream D2 is consequently transformed into a bit stream in which the SDLC flag F usually coded 01111110 (i.e., 7E in hexadecimal), will never be applied to the transmitting Data Communication Equipment DCE1 attached to the terminal provided with the highest priority level and operating in SDLC mode. When the beginning of an SDLC message, i.e., 011111101 (FA in hexadecimal), is decoded by DECODER 1, then the switch SW1 is set to its lowest position, S1. The transmit clock signal C2 is interrupted which stops any further bit being provided through D2 to the transmitter shift reg...