Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Read-Only Memory Array

IP.com Disclosure Number: IPCOM000041915D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 92K

Publishing Venue

IBM

Related People

Kalter, H: AUTHOR [+2]

Abstract

An improved read-only memory array is disclosed having a compact integrated circuit layout for an "AND array"-type topology. Fig. 1 illustrates the layout for the circuit whose schematic diagram is illustrated in Fig. 2. The integrated circuit is formed in a silicon semiconductor substrate with the diffusions labeled Dij arranged in standard matrix notation, as is seen in Fig. 1. Diffusions D1,1 and D11,1 are connected to the overlying vertical metal bit line BL1 on a top layer by means of via connections. The diffusion D6,1 is connected by means of a via connection to a top layer metal line CL1 . D1,2 and D11,2 are connected by means of via connections to the top layer metal line BL2 . A series-connected array of FET devices 1, 2, 3, 4 and 5 are connected in series between the diffusion D1,1 and the diffusion D6,1 .

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Read-Only Memory Array

An improved read-only memory array is disclosed having a compact integrated circuit layout for an "AND array"-type topology. Fig. 1 illustrates the layout for the circuit whose schematic diagram is illustrated in Fig. 2. The integrated circuit is formed in a silicon semiconductor substrate with the diffusions labeled Dij arranged in standard matrix notation, as is seen in Fig. 1. Diffusions D1,1 and D11,1 are connected to the overlying vertical metal bit line BL1 on a top layer by means of via connections. The diffusion D6,1 is connected by means of a via connection to a top layer metal line CL1 . D1,2 and D11,2 are connected by means of via connections to the top layer metal line BL2 . A series-connected array of FET devices 1, 2, 3, 4 and 5 are connected in series between the diffusion D1,1 and the diffusion D6,1 . FET device 1 is formed between the diffusions D1,1 and D2,1 which serve respectively as the drain and source of the FET device 1, its gate being formed by the polycrystalline silicon gate electrode WS1 which occupies a level intermediate between the diffusion level in the silicon substrate and the overlying metal layer level. The FET device 2 has its drain formed by the diffusion D21 and its source formed by the diffusion D31 and its gate is the polycrystalline silicon line WL11 . The FET device 3 has its drain as the diffusion D31 and its source as the diffusion D41 and its gate is the polycrystalline silicon line WL12 . The FET device 4 has its drain as the diffusion D41, its source as the diffusion D51, and its gate as the polycrystalline silicon line WL13 . The FET device 5 has its drain as the diffusion D51, its source as the diffusion D61, and its gate as the polycrystalline silicon gate line WL14 . The serially connected FET devices 1, 2, 3, 4 and 5 are selectively programmed by ion implanting the same conductivity type dopant as is used for the source and drain for the device. In N channel technology, for example, with a P-type silicon substrate and N-type diffusions, a particular FET device will be programmed at the time of manufacture by ion implanting N-type dopant into its channel region in order to make that device a depletion-mode device. The absence of an ion implantation step in the channel region of a particular FET device leaves that device as an enhancement-mode device. The technique for distinguishing between enhancement-mode and depletion-mode devices and therefore between a preprogrammed 1 or 0 will become more evident in the following description. Referring now to Fig. 2 which is the circuit schematic diagram of the read-only memory array and Fig. 3 which shows a time diagram of its operation, the...