Browse Prior Art Database

Integrated LSSD Clock and Reset Control

IP.com Disclosure Number: IPCOM000041918D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Brown, MD: AUTHOR [+2]

Abstract

Use of level sensitive scan design (LSSD) logic chips requires added external logic for power-on reset (POR) and clocking. The figure shows circuitry to overcome this disadvantage. POR and clocking circuitry is entirely contained on the chip. POR is the standard pulse normally applied to circuitry. The nonoverlapping clock generator is the usual circuit found in LSSD literature. The timing circuitry consists of LSSD shift register latches (SRLs) and decodes for the timing states T1-TN and is initialized during POR by forcing its SRL steering logic to the desired initial state and clocking it with the nonoverlapping clock generator. The sequencing circuit, SRLs 1 and 2, is also clocked by the nonoverlapping clock generator.

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Integrated LSSD Clock and Reset Control

Use of level sensitive scan design (LSSD) logic chips requires added external logic for power-on reset (POR) and clocking. The figure shows circuitry to overcome this disadvantage. POR and clocking circuitry is entirely contained on the chip. POR is the standard pulse normally applied to circuitry. The nonoverlapping clock generator is the usual circuit found in LSSD literature. The timing circuitry consists of LSSD shift register latches (SRLs) and decodes for the timing states T1-TN and is initialized during POR by forcing its SRL steering logic to the desired initial state and clocking it with the nonoverlapping clock generator. The sequencing circuit, SRLs 1 and 2, is also clocked by the nonoverlapping clock generator. During POR, it forces the C clocks off and the A and B clocks on for all other chip SRLs except those in the timing circuit. The sequencing and timing SRLs are the first SRLs in the LSSD scan path. After the timing circuit initializes, it provides a known level that is "flushed" down the scan path, initializing the rest of the chip. When the POR signal drops, the A and B clocks are sequenced off before the C clocks come active and the timing circuit starts from its initialized state. The timing circuit, therefore, keeps the scan path conditioned until after the A and B clocks are sequenced off, ensuring a reliable chip initialization. During functional operation, the LSSD A, B, and C clocks, as well as sc...