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Optimized Precompensation Circuit

IP.com Disclosure Number: IPCOM000041919D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Danen, JA: AUTHOR [+2]

Abstract

The figure illustrates a method using delay elements to accomplish precompensation in data encode circuits. Delay 5, between the encoded data register and the balance of the precompensation circuitry, is used to allow the register outputs to stabilize. The remaining delay circuit, 6 and 7 set the value of precompensation. The outputs of the delay elements are "ANDed" with the bit definitions in the encoded data register by AND circuits 10, 11, 12. The outputs of AND circuits 10, 11, 12 and inverter 13 are summed by the output OR circuit 15 so that the leading edge of the pulse at the output line 16 is moved in accordance with the data pattern requirements. This design tolerates a wide range of precompenstion values and delay generator types.

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Optimized Precompensation Circuit

The figure illustrates a method using delay elements to accomplish precompensation in data encode circuits. Delay 5, between the encoded data register and the balance of the precompensation circuitry, is used to allow the register outputs to stabilize. The remaining delay circuit, 6 and 7 set the value of precompensation. The outputs of the delay elements are "ANDed" with the bit definitions in the encoded data register by AND circuits 10, 11, 12. The outputs of AND circuits 10, 11, 12 and inverter 13 are summed by the output OR circuit 15 so that the leading edge of the pulse at the output line 16 is moved in accordance with the data pattern requirements. This design tolerates a wide range of precompenstion values and delay generator types. Logic gate delays or delay lines can be used without a change in the overall configuration.

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