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LVI Receiver Circuit With Improved Noise Margin

IP.com Disclosure Number: IPCOM000041934D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Mayo, DM: AUTHOR

Abstract

A low voltage inverter (LVI) receiver is disclosed which is up-level, down-level and threshold-level compatible with standard LVI off-chip driver and internal circuits. A standard LVI internal circuit is shown in Fig. 1. The receiver of Fig. 2 has improved noise margin and is up-, down-, and threshold-level compatible with the LVI internal circuit. Thus, the receiver can receive signals from on or off-chip. The operation of the receiver is described in 3 regions of operation, as shown in Fig. 3. T2 is assumed off. Region 1 VIN is low enough so that T1 is off. VOUT is 2.0 V - flows through RB, D1, D2 and RE, providing an offset voltage across RE . This offset voltage tends to raise the threshold of the gate. To obtain noise margin, the gain of the receiver (NRC/RE) is made higher than the gain of the LVI internal circuit.

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LVI Receiver Circuit With Improved Noise Margin

A low voltage inverter (LVI) receiver is disclosed which is up-level, down-level and threshold-level compatible with standard LVI off-chip driver and internal circuits. A standard LVI internal circuit is shown in Fig. 1. The receiver of Fig. 2 has improved noise margin and is up-, down-, and threshold-level compatible with the LVI internal circuit. Thus, the receiver can receive signals from on or off- chip. The operation of the receiver is described in 3 regions of operation, as shown in Fig. 3. T2 is assumed off. Region 1 VIN is low enough so that T1 is off. VOUT is 2.0 V - flows through RB, D1, D2 and RE, providing an offset voltage across RE . This offset voltage tends to raise the threshold of the gate. To obtain noise margin, the gain of the receiver (NRC/RE) is made higher than the gain of the LVI internal circuit. This increase in gain tends to lower the threshold of the receiver relative to an internal circuit. However, when properly designed, the offset voltage which is across RE, exactly cancels the effect of increased gain on the threshold. Although the receiver has more gain than an internal circuit, the thresholds are the same. The offset voltage across RE also appears across RO via a current mirror consisting of RB, D2, D1, TO and RO . The mirrored current flows through TP and provides the same function as the bleeder resistor RBL in the internal circuit. Region 2 VIN is in the transition region. T1 i...