Browse Prior Art Database

Microcode Design of Integrated Channels for Easy Migration to Non-Integrated Channels

IP.com Disclosure Number: IPCOM000041941D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Bolan, JE: AUTHOR

Abstract

Referring to Fig. 1, some computer system processors include channels that are integrated with an IPU, and a trap mechanism is is utilized to cycle steal from the IPU (Instruction Processor Unit) in order to accomplish its various functions, such as data transfer, exceptional conditions, etc. The prior-art microcode design must use hardware, shared between the CHANNEL and IPU resources, to perform the architected functions of the microcode. This prevents the IPU from performing actual instruction processing while the channel is cycle stealing. As a result, a separate channel engine could be utilized for the processors of the prior art, as the channel functions become more and more complex (as in the IBM System/370XA mode). Referring to Fig.

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Microcode Design of Integrated Channels for Easy Migration to Non- Integrated Channels

Referring to Fig. 1, some computer system processors include channels that are integrated with an IPU, and a trap mechanism is is utilized to cycle steal from the IPU (Instruction Processor Unit) in order to accomplish its various functions, such as data transfer, exceptional conditions, etc. The prior-art microcode design must use hardware, shared between the CHANNEL and IPU resources, to perform the architected functions of the microcode. This prevents the IPU from performing actual instruction processing while the channel is cycle stealing. As a result, a separate channel engine could be utilized for the processors of the prior art, as the channel functions become more and more complex (as in the IBM System/370XA mode). Referring to Fig. 2, in order to minimize or eliminate these disadvantages of the prior art, a microcode design for 370XA architecture is provided. By taking advantage of the processor internal interrupt mechanism, which passes control to the microcode between instructions, the proposed microcode design allows all channel functions to be initiated from the internal interrupt handler, including all I/O instruction queuing, path management, I/O interrupt queuing, and internal busy queue handling. By designing the microcode in this fashion, all these functions mentioned previously are easily migrated to a separate channel engine. The internal interrupt bit, that...