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Illegal Logic Level Sensing Circuit

IP.com Disclosure Number: IPCOM000041942D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Daghir, KS: AUTHOR [+2]

Abstract

An illegal logic level is defined herein as the input voltage level which falls between the binary logic levels '1' and '0' and of a value sufficiently close to the threshold voltage to cause an uncertainty in the output. In order to address a cell or group of cells in a random-access memory (RAM) array, for example, logic levels '1' and '0' are applied to true and complement generators for decoding the signals. If an illegal logic level is applied, under certain conditions, the RAM array will lose its data-retention capability. Disclosed herein is a circuit which solves the above problem by detecting the illegal logic level and taking the necessary corrective action.

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Illegal Logic Level Sensing Circuit

An illegal logic level is defined herein as the input voltage level which falls between the binary logic levels '1' and '0' and of a value sufficiently close to the threshold voltage to cause an uncertainty in the output. In order to address a cell or group of cells in a random-access memory (RAM) array, for example, logic levels '1' and '0' are applied to true and complement generators for decoding the signals. If an illegal logic level is applied, under certain conditions, the RAM array will lose its data-retention capability. Disclosed herein is a circuit which solves the above problem by detecting the illegal logic level and taking the necessary corrective action. One way of accomplishing this is to convert the legal logic levels '1' and '0' to, for example, logic level '1' and convert any illegal logic level to logic level '0'. The circuit shown schematically in Fig. 1 precisely achieves this. When the logic level input is either a '1' or '0', a logic '0' is produced at node L0 because of the collector dot. Consequently, the logic level at the output V0 will be '1'. When the logic level input is an illegal logic level (i.e., the input signal is near the threshold) the voltage at node L0 will also be near the threshold and, by design, it is sufficiently high to bring the output V0 down to logic level '0'. Thus, whenever the logic levels at the input are '0' or '1' (i.e., legal inputs) the output at V0 will be '1', and whene...