Browse Prior Art Database

Protective Circuit

IP.com Disclosure Number: IPCOM000041945D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Abramson, P: AUTHOR [+2]

Abstract

This article discloses a circuit arrangement for monitoring the output signal from a power supply and to inhibit the output signal if the signal falls outside a predetermined range. The circuit uses two comparators and a resistor divider network to control a transistor switch. The output signal from the transistor switch represents the signal from the power supply. With reference to the drawing, resistor R1 and zener diode D1 are connected in series to a power supply VCC . The series combination forms a reference voltage Vref at node N1. Vref is connected to the positive input and negative inputs of C1 and C2, respectively. A resistive network comprised of R2, R3 and R4 forms two voltages fed to C1 and C2 for comparison with Vref .

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Protective Circuit

This article discloses a circuit arrangement for monitoring the output signal from a power supply and to inhibit the output signal if the signal falls outside a predetermined range. The circuit uses two comparators and a resistor divider network to control a transistor switch. The output signal from the transistor switch represents the signal from the power supply. With reference to the drawing, resistor R1 and zener diode D1 are connected in series to a power supply VCC . The series combination forms a reference voltage Vref at node N1. Vref is connected to the positive input and negative inputs of C1 and C2, respectively. A resistive network comprised of R2, R3 and R4 forms two voltages fed to C1 and C2 for comparison with Vref . Should the N3 voltage drop below Vref, the comparator C1 output goes high, turning on transistor Q1. Similarly, should the N2 voltage rise above Vref, the comparator C2 output does the same. N2 and N3 voltage are merely scaled versions of the monitored voltage Vcc . Hence, the C1 and C2 outputs will both be down if Vcc is within the bounds determined by the R2, R3, R4 divider network. If the need arises, other inputs can be fed into the base of Q1 to control the output therefrom.

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