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Two-Tier Error Correcting Code for Memories

IP.com Disclosure Number: IPCOM000041946D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Wortzman, D: AUTHOR

Abstract

The correction ability of single error correct and double error detect (SEC/DEC) codes is improved by partitioning the memory into two regions of ECC bit positions. One region has greater than nominal correctability into which known faulty memory bits are mapped by address or data steering techniques. The other region has less than nominal correctability into which no known faulty memory bits are mapped. Conventional error correcting codes (ECCs) treat all bits of an ECC word in the same manner. The code which is described here, on the contrary, is very correctable for a few of the bits and is much less correctable for the remainder of the bits. By logically moving all known faulty bits to the high correctability region, the overall correctability of the code is improved.

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Two-Tier Error Correcting Code for Memories

The correction ability of single error correct and double error detect (SEC/DEC) codes is improved by partitioning the memory into two regions of ECC bit positions. One region has greater than nominal correctability into which known faulty memory bits are mapped by address or data steering techniques. The other region has less than nominal correctability into which no known faulty memory bits are mapped. Conventional error correcting codes (ECCs) treat all bits of an ECC word in the same manner. The code which is described here, on the contrary, is very correctable for a few of the bits and is much less correctable for the remainder of the bits. By logically moving all known faulty bits to the high correctability region, the overall correctability of the code is improved. No additional bits are required over conventional SEC/DET codes. The following sequence of figures can be used to explain the ECC scheme. Fig. 1 shows an H Matrix with no errors. There are 32 information bits and 8 check bits stored on 10 chips 1 through 0. Each chip has 4 bits 1-4. Fig. 2, chip 5/bits develop a soft error. Syndrome bits 2, 6, and 8 turn on, indicating to the logic which bit is in error. It is corrected, and since the error is soft, the failing bit is fixed. Fig. 3, chip 3 fails, bits 2 and 3 are in error. Syndrome bits 2 and 3 are turned on, indicating that bits 2 and 3 are in error; however, there is no indication of which chip is ba...