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Polysilicon Base Transistor Sidewall Thickness Measurement Technique

IP.com Disclosure Number: IPCOM000041949D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Dockerty, RC: AUTHOR

Abstract

In a polysilicon base transistor of the type shown in a schematic cross-sectional representation in Fig. 1, it is important to know the physical separation at the wafer level between the P+ polysilicon base contact (edge A) and the emitter metal contact (edge B). This wafer level separation between edges A and B, known as sidewall thickness SW, differs from the mask/design level separation due to process biases associated with the fabrication of edges A and B. If A1 and B1 represent the mask level measurements corresponding to edges A and B, respectively, then where (A - B) wafer is the wafer level separation between edges A and B and WA and WB are the process biases associated, respectively, with the fabrication of the polysilicon base and emitter contact.

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Polysilicon Base Transistor Sidewall Thickness Measurement Technique

In a polysilicon base transistor of the type shown in a schematic cross-sectional representation in Fig. 1, it is important to know the physical separation at the wafer level between the P+ polysilicon base contact (edge A) and the emitter metal contact (edge B). This wafer level separation between edges A and B, known as sidewall thickness SW, differs from the mask/design level separation due to process biases associated with the fabrication of edges A and B. If A1 and B1 represent the mask level measurements corresponding to edges A and B, respectively, then where (A - B) wafer is the wafer level separation between edges A and B and WA and WB are the process biases associated, respectively, with the fabrication of the polysilicon base and emitter contact. Disclosed herein is a nondestructive technique of determining WA and WB and thereby SW. To determine WA, a set of n polysilicon base resistor structures of the configuration shown in Fig. 2 and having a fixed length L and varying width Wn are formed on the wafer and their resistance values Rn are measured. Rn is related to the Wn and L by the equation where pp is the polysilicon sheet resistance. Since the polysilicon resistors (Fig. 2) each have two edges and their length is significantly larger than the width where (Wn)mask is the mask level width of the n-th resistor. By combining equations (1) and (2), there is obtained

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