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Hybrid Memory Cell for Two Port Rams

IP.com Disclosure Number: IPCOM000041990D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

A static latch used in a random-access memory (RAM) macro may have the configuration shown in Fig. 1. This cell can be used in a two-port RAM and can easily interface with logic. For larger RAM macros further optimization is desirable. A hybrid two-port RAM cell is shown in Fig. 2. The advantages of this cell are: (1) retains the two-port capability and easy interface to logic; (2) less devices and wirings - smaller silicon area; (3) avoids the potential problems of direct base coupling; (4) potentially faster; and (5) bit select is possible for both write and read. The operation of this hybrid cell is illustrated in Fig. 3. Write is by emitter coupling, and read is by Schottky coupling. Some simplistic TTL peripherals are assumed which accept the regular logic levels.

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Hybrid Memory Cell for Two Port Rams

A static latch used in a random-access memory (RAM) macro may have the configuration shown in Fig. 1. This cell can be used in a two-port RAM and can easily interface with logic. For larger RAM macros further optimization is desirable. A hybrid two-port RAM cell is shown in Fig. 2. The advantages of this cell are: (1) retains the two-port capability and easy interface to logic; (2) less devices and wirings - smaller silicon area; (3) avoids the potential problems of direct base coupling; (4) potentially faster; and (5) bit select is possible for both write and read. The operation of this hybrid cell is illustrated in Fig. 3. Write is by emitter coupling, and read is by Schottky coupling. Some simplistic TTL peripherals are assumed which accept the regular logic levels. Four voltage levels are relevant to this hybrid cell operation:

(Image Omitted)

Simultaneous read/write can be performed at two different addresses. For simultaneous read/write at the same address, some additional logic is needed. Logic will depend on system requirement of whether it should be "write through" or "read first". In case of "write through", i.e., read data should be the current write data, some logic such as the following is needed: Input signal RS (read select) is replaced by RS AND W (read select but not write select). A signal RA (read -S ahead) = (RS AND WS) is generated which will gate the write data into the read data Bus. In Fig. 3, word line...