Browse Prior Art Database

True/Complement Shift-Array Multiplier

IP.com Disclosure Number: IPCOM000041991D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 34K

Publishing Venue

IBM

Related People

Smith, CD: AUTHOR [+2]

Abstract

The shift-array multiplier Fig. 1 implements part of a known algorithm that is associated with the multiplier (MPLER) decoder, the multiplicand (MPCMD) shift true/complement (T/C) gates, and the adder, (see Fig. 3 of U. S. Patent 4,228,520, for example). It uses cascode current switch logic (CCSL) and results in one-half the number of delay blocks for an array of conventional full adders. The multiplier facilitates design, layout and wiring than is otherwise the case with some other known types. The multiplier (Fig. 1) is described in a 28 x 28-bit array configuration example with a 56-bit product (XY) output. The bits X0-X27 and Y0-Y27 of the multiplicand and multiplier numbers X and Y, respectively, are located in respective registers 1 and 2.

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True/Complement Shift-Array Multiplier

The shift-array multiplier Fig. 1 implements part of a known algorithm that is associated with the multiplier (MPLER) decoder, the multiplicand (MPCMD) shift true/complement (T/C) gates, and the adder, (see Fig. 3 of U. S. Patent 4,228,520, for example). It uses cascode current switch logic (CCSL) and results in one-half the number of delay blocks for an array of conventional full adders. The multiplier facilitates design, layout and wiring than is otherwise the case with some other known types. The multiplier (Fig. 1) is described in a 28 x 28-bit array configuration example with a 56-bit product (XY) output. The bits X0-X27 and Y0-Y27 of the multiplicand and multiplier numbers X and Y, respectively, are located in respective registers 1 and 2. The Y bits are decoded in a decoder system DECODER 3 which provides output control signals that are processed with the X bits by the shift register array 4. DECODER 3 has decoder/remember logic (Fig. 2 in [1]). As described [1], DECODER 3 transforms pairs of Y bits, i.e., the least significant bit (LSB) pair Y0/Y1, the next LSB pair Y2/Y3,...., and the most significant bit (MSB) pair Y26/Y27, into 14 corresponding sets 301-314 of four control lines each, i.e., set 301 of lines C(-X0), C(-X1), C(+X0), C(+0), set 302 of lines C(-X2), C(X3), C(+X2), C(+0), ...., and set 314 of lines C(-X26), C(- X27), C(+X26), C(+0), respectively. Each set of control lines 301-314 controls one of the 14 rows of the shift register array 4. Output 315 of DECODER 3 controls the FINAL ADDER 5. Array 4 is a matrix of logical blocks or cells, 29 columns wide by 14 rows high. Each row does logical combinations of SHIFT, ADD, and COMPLEMENT. Also, each row feeds its respective carry-out and its propagate outputs C and P to the carry and propagate inputs, respectively, of certain cells of the next succeeding row (see [2]). The COMPLEMENT and ADD combination is the first part of a Twos-complement subtraction. The HOT ONES ADDER 6 completes the Twos-complement subtraction by adding a One to the appropriate array output whenever a COMPLEMENT and ADD is done in array 4, thereby transforming the Ones-complement resulting from the last-mentioned COMPLEMENT and ADD combination into the Twos complement. The FINAL ADDER 5 adds the multiplicand (X) to the higher-order partial product bits of array 4 when a FINAL REMEMBER is generated by DECODER 3 on line 315. SUPPRESS CARRY logic 7 suppresses the car...