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True/Complement Shift-Array Multiplier Cell

IP.com Disclosure Number: IPCOM000041992D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Smith, CD: AUTHOR

Abstract

A true/complement shift-array multiplier cell 400 (Fig. 1) is configured in differential cascode current switch circuit technology and is compatible with the multiplier array and decoder described in the preceding article and following article, respectively. The cells are arranged in an XY matrix array, as shown in the preceding article. The bits of the multiplicand number X are associated with the columns of the array. The rows of the array are controlled by mutually exclusive sets of four control signals derived from paired successive order bits of the multiplier number Y by the decoder of the following article. The cell provides a reduction in devices and delays in comparison to other known types of cells. The cell has four series-connected cascode current switch levels 101-104.

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True/Complement Shift-Array Multiplier Cell

A true/complement shift-array multiplier cell 400 (Fig. 1) is configured in differential cascode current switch circuit technology and is compatible with the multiplier array and decoder described in the preceding article and following article, respectively. The cells are arranged in an XY matrix array, as shown in the preceding article. The bits of the multiplicand number X are associated with the columns of the array. The rows of the array are controlled by mutually exclusive sets of four control signals derived from paired successive order bits of the multiplier number Y by the decoder of the following article. The cell provides a reduction in devices and delays in comparison to other known types of cells. The cell has four series-connected cascode current switch levels 101-104. A set of the mutually exclusive control signals C(-XN), C(-XN+1), C(+XN), and C(+0), from the aforementioned decoder are fed to the respective inputs of the gates of level 101. Because these signals are mutually exclusive, their NOT counterparts and consequently gates therefor in level 101 are not required. In the other levels 102-104, the input signals are fed thereto in their true and complementary forms. Accordingly, appropriate individual gates are used for each. Level 102 is responsive to a pair of multiplicand bits, i.e., the particular bit Xi associated with the particular column of the array in which the cell is located and the next successive higher-order bit Xi+1 of the next successive column. The inputs PI and NOT PI of level 103 are fed by the propagate signal and its NOT counterpart of a cell located in the column associated with the Xi+2 multiplicand bit of the preceding row of the array. The inputs CI and NOT CI of level 104 are fed by the carry-out signal and its NOT counterpart from a cell located in the column associated with the Xi+1 multiplicand bit of the pre...