Browse Prior Art Database

True/Complement Shift-Array Multiplier Decoder

IP.com Disclosure Number: IPCOM000041993D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Smith, CD: AUTHOR

Abstract

The decoders 200 (Fig. 2) are configured in differential cascode current switch circuit technology (Fig. l) for compatibility with the multiplier array and the array's cells described in the preceding two articles. In the decoder system (Fig. 2), one decoder 200 is provided for processing each pair of successive order bits Y0/Y1, Y2/Y3, ... YN/YN+1 of the multiplier number Y which contains multiple bits, e.g., twenty-eight bits, N being 0, 2, 4,....26. The decoder 200 converts the two bits into a set of four control signals, e.g., the four control signals C(-XN), C(-XN+1), C(+XN), C(+0).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

True/Complement Shift-Array Multiplier Decoder

The decoders 200 (Fig. 2) are configured in differential cascode current switch circuit technology (Fig. l) for compatibility with the multiplier array and the array's cells described in the preceding two articles. In the decoder system (Fig. 2), one decoder 200 is provided for processing each pair of successive order bits Y0/Y1, Y2/Y3, ... YN/YN+1 of the multiplier number Y which contains multiple bits, e.g., twenty-eight bits, N being 0, 2, 4,....26. The decoder 200 converts the two bits into a set of four control signals, e.g., the four control signals C(-XN), C(-XN+1), C(+XN), C(+0). Each set of the resulting fourteen sets 301-314 in turn is fed to a row of the aforementioned array (not shown) where it is processed by the cells (not shown) of the row with the bits of the multiplicand number X that are being fed to the array's columns. A remember logic circuit 300 (Fig. 2) also decodes the paired signal bits, e.g., YN and YN+1, and provides a remember control signal R (ADD ONE) to the decoder 200 and remember 300 of the next row. The control signal R of the last remember circuit is fed, via conductor 315, to the FINAL ADDER (not shown) of the multiplier array. The remember input 350 of the top remember 300 is set to a logical "0". The use of remember codes and their decoding function is described, for example, in U.S. Patent 4,228,520. Thus, the inputs YN, YN+1, and R have weights corresponding to the weights of their counterparts in the algorithm of U.S. Patent 4,228,520. Each decoder 200 has three series-connected cascode current switch levels 11-13 (Fig. 1). The particular two successive order bits YN and YN+1 together with their respective NOT counterparts are fed to the inputs of appropriate gates of levels 12 and 11, respectively. The remember bits R and R NOT from the remember 300 of the preceding row (Fig. 2) are fed to appropriate gates of level 13. The algorithmic function provided by a decoder 200 for the different dual ended input signal combinations and their correlated output signals, and typical active and inactive voltage response levels of its cascode levels are indicated in Table 1. Table 2 is a truth table for the logic circuit 2...