Browse Prior Art Database

High Performance Overlapped Pipeline Machine

IP.com Disclosure Number: IPCOM000042008D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Yamour, YJ: AUTHOR

Abstract

This high performance overlapped pipeline machine can execute instruction mixes in/out of sequence fashion through the use of a Recovery and Execute Buffer (REB) of the circular wraparound type. During the decode cycle of an instruction, the image of the instruction along with the contents of R1 are transferred into REB. R1 is the register the contents of which may be modified when the instruction is executed. In addition, REB contains the necessary information to ascertain full machine recovery, such as part of the instruction counter, among others. On the subsequent cycle REB can provide one of the operands to the execution unit which then executes the instruction. This machine organization is shown in the figure.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 59% of the total text.

Page 1 of 2

High Performance Overlapped Pipeline Machine

This high performance overlapped pipeline machine can execute instruction mixes in/out of sequence fashion through the use of a Recovery and Execute Buffer (REB) of the circular wraparound type. During the decode cycle of an instruction, the image of the instruction along with the contents of R1 are transferred into REB. R1 is the register the contents of which may be modified when the instruction is executed. In addition, REB contains the necessary information to ascertain full machine recovery, such as part of the instruction counter, among others. On the subsequent cycle REB can provide one of the operands to the execution unit which then executes the instruction. This machine organization is shown in the figure. The instructions are transferred into REB sequentially but can be executed out of sequence, particularly underneath memory referencing instructions still pending their execution. As instructions enter REB, they are marked with either flag, Valid (VLD) or Invalid (INV), indicating whether an instruction has successfully completed or is pending execution, respectively. New instructions can enter the REB ahead of its top pointer position but not surpassing a pending execution earlier instruction. Instructions I2, I3,....In following the wraparound instruction I1 can be possibly executed out of sequence, without regard to any subsequent conflicts, such as data dependencies, interlocks, and others. Thus instruct...