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CRT Vertical Timebase Utilizing Programmable Magnitude Voltage Steps

IP.com Disclosure Number: IPCOM000042022D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 4 page(s) / 49K

Publishing Venue

IBM

Related People

Cole, TG: AUTHOR [+3]

Abstract

Accurate line spacing on a CRT display is achieved by using a CRT vertical timebase circuit which, instead of the customary ramp voltage, produces a staircase voltage with accurately defined step height. Attached logic enables line skips of a range of magnitudes to be automatically invoked, depending on the display contents of the screen, in order to avoid scanning lines in blank sections of the screen (a situation often encountered in menu-driven applications). With this arrangement, the screen may be scanned at a higher rate, resulting in an increase in screen brightness without the need for increased beam current or more efficient screen phosphors. The vertical timebase circuit shown in Fig.

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CRT Vertical Timebase Utilizing Programmable Magnitude Voltage Steps

Accurate line spacing on a CRT display is achieved by using a CRT vertical timebase circuit which, instead of the customary ramp voltage, produces a staircase voltage with accurately defined step height. Attached logic enables line skips of a range of magnitudes to be automatically invoked, depending on the display contents of the screen, in order to avoid scanning lines in blank sections of the screen (a situation often encountered in menu-driven applications). With this arrangement, the screen may be scanned at a higher rate, resulting in an increase in screen brightness without the need for increased beam current or more efficient screen phosphors. The vertical timebase circuit shown in Fig. 1 uses the inherent accuracy and analogue properties of a 'cup and bucket' circuit to generate the accurately defined stepped voltage waveform required to drive the CRT. The circuit receives as input horizontal synch pulses at input terminal 1 and the staircase output voltage is obtained from output terminal 2. The voltage waveforms appearing at the various marked nodes A, B and C in Fig. 1 are shown in Fig. 2 in response to horizontal synch pulses applied to input terminal 1. When the horizontal synch applied to input terminal 1 goes positive, transistor T1 is switched into saturation and node B is forced negative by the supply voltage V STEP. Operational amplifier 3 drives node C high, diverting constant current I2 from transistor T5 through transistor T4. This current is current mirrored via transistors T7 and T6 to node B, which is linearly restored to ground (virtual) by the constant current I2. The amount of charge required to restore node B to ground potential is duplicated in the ratioing mirror array, formed by transistors T8 to T13, which charges the bucket capacitor C2. Thus, the charge originally stored in the cup capacitor C1 is transferred to the bucket capacitor C2 in a programmable ratio determined by the selection of the current mirrors. By making V STEP large compared with any temperature variations in the saturation voltage of transistor T1, and by using good temperature independence of the current mirrors, the step height of the resultant output waveform at output terminal 2 is well controlled. Any multiple of the step height can be accomplished by switching in or out any combination of mirrors in the mirror array. To provide interlace, for example, a half step is achieved by disabling transistors T9 to T13 inclusive. A full step is achieved by enabling transistor T9 with transistors T10 to T13 inclusive disabled. Any integer line skip up to fifteen can be achieved by enabling any combination of the transistors T10 to T13. The charge on the cup capacitor C1 is restored when the horizontal synch returns to ground and transistor T1 turns off. Initially, the cup capacitor charges through resistor R1 and diode D1. As node B goes positive, the operational am...