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Highly Concurrent Engineering/Scientific Machine Organization

IP.com Disclosure Number: IPCOM000042025D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Grohoski, GF: AUTHOR [+2]

Abstract

Engineering/Scientific Processors consist of multi-processing units, such as Fixed-Point, Floating-Point and Vector Units, that process, possibly in parallel, their respective class of instructions. All units, and particularly the Scalar ones, try to achieve the highest possible performance. Often, processing units perform work in order to assist other units, the performance of which is critical. For example, the Fixed-Point Unit (FPU) computes the addresses needed for fetching/storing memory floating-point operands. This address generation consumes many cycles, depending on the number of floating point memory references, which in turn results in lower Scalar performance. Since the Scalar performance is of utmost importance, this inter-unit assist does not offer a viable solution.

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Highly Concurrent Engineering/Scientific Machine Organization

Engineering/Scientific Processors consist of multi-processing units, such as Fixed-Point, Floating-Point and Vector Units, that process, possibly in parallel, their respective class of instructions. All units, and particularly the Scalar ones, try to achieve the highest possible performance. Often, processing units perform work in order to assist other units, the performance of which is critical. For example, the Fixed-Point Unit (FPU) computes the addresses needed for fetching/storing memory floating-point operands. This address generation consumes many cycles, depending on the number of floating point memory references, which in turn results in lower Scalar performance. Since the Scalar performance is of utmost importance, this inter-unit assist does not offer a viable solution. This article proposes a solution that achieves cost-effective higher performance in both Scalar and Floating-Point computations. In this, a fixed-point General-Purpose Register (GPR) copy is maintained in the Floating-Point Unit (FLPU), which is used for address generation. The cycle activities of the proposed organization are shown below with reference to an exemplary instruction stream consisting of fixed-point and floating-point operations. Instruction Stream

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D denotes a decode cycle, AG an address generation cycle, C1 a Cache 1 cycle, C2 a Cache 2 cycle, E an execute cycle, and PA a Put-Away cycle. In orde...