Browse Prior Art Database

Self-Adjusting Analog Ejection-Injection Testing

IP.com Disclosure Number: IPCOM000042039D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 90K

Publishing Venue

IBM

Related People

Blum, A: AUTHOR

Abstract

The so-called ejection-injection mechanism does not require any slave latches for information buffering during the shifting process. The output of the preceding single latch is fed to a shift input of the succeeding single latch. The latch input AI-gate is provided with a separate gate signal (Fig. 1). In order to eject the contents of all single latches of the chain, ejection gating signals will be applied to the individual chain input AI-gates of the single latches, as shown in Fig. 2.

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Self-Adjusting Analog Ejection-Injection Testing

The so-called ejection-injection mechanism does not require any slave latches for information buffering during the shifting process. The output of the preceding single latch is fed to a shift input of the succeeding single latch. The latch input AI-gate is provided with a separate gate signal (Fig. 1). In order to eject the contents of all single latches of the chain, ejection gating signals will be applied to the individual chain input AI-gates of the single latches, as shown in Fig. 2.

So, while the leading edge of the ejection gating signals propagates from one single latch to the next one starting from the right-hand end of the chain, the ejection gate inputs of the already passed single latches stay active for a longer time, allowing analog propagating of the single latch information to the right-hand end of the chain of the latches. In order to make this mechanism work the leading edge of the ejection gate should merely not appear at the right-hand one of two adjacent single latches later (or significantly later because of the positive inherent latch delay) than at the left-hand single latch. In any case the ejection gates could appear at all single latches at exactly the same time. This would result in an ejection time of all latches of the chain within a single delay of the latch connection path. The theoretically resulting ejection time of all latches might be even shorter if the ejection gates arrive slightly earlier at the latches of the left-hand end of the chain in a time staggered fashion, which can be tolerated because of the positive inherent delay of the latches. In this case the succeeding overlapped injection mode can start earlier. In the following, for practical implementation only those cases will be considered where the ejection gates arrive at the right-hand latches exactly at the same time as, or earlier than, at the left-hand latches. The injection process will be accomplished analogously by deactivating the ejection gates in a staggered fashion from the right to the left, or even at all latches simultaneously, depending on the tester control mechanism implemented. Therefore, the ejection gating signals will also be called ejection- injection gating signals. For buffering purposes in case of functional pipelining the logic between latches usually can be reduced to a simple move function. Similar to the functional utilization of the slave latches in the LSSD (level sensitive scan design) mode, the single latches can also be used within the context of the proposed technique for the required buffering application functions. In this case the single latches can even be simplified by combining the functional data latch input with the eject-inject (shift) input to a single AI-gate. The data path is then shared with the eject-inject path, and the functional clock and the ejection- injection gate inputs are "dot-ORed" in case the individual signal sources are electr...