Browse Prior Art Database

High Speed Three-Level Hierarchy Storage

IP.com Disclosure Number: IPCOM000042043D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Baier, E: AUTHOR [+2]

Abstract

A new store architecture on a chip with unique operation modes is disclosed which contains three independent storages on the same chip. The three level hierarchy storage L1 - L3 shown refers to a 1-bit organized FET chip, i.e., one DI, DO (DIO) pad. A 4-bit organization is possible, too, but will not be covered. Since the storage levels L1 to L3 can be accessed more or less independently of each other, versatile applications for the system designer are possible. The figure and the following table show the three levels L1 - L3 of a storage hierarchy on a chip featuring different storage sizes and operation modes (read and write). (Image Omitted) Each operation mode is controlled by its own timing chain. The three timing chains are activated by RAS, CAS, and data gate DG.

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High Speed Three-Level Hierarchy Storage

A new store architecture on a chip with unique operation modes is disclosed which contains three independent storages on the same chip. The three level hierarchy storage L1 - L3 shown refers to a 1-bit organized FET chip, i.e., one DI, DO (DIO) pad. A 4-bit organization is possible, too, but will not be covered. Since the storage levels L1 to L3 can be accessed more or less independently of each other, versatile applications for the system designer are possible. The figure and the following table show the three levels L1 - L3 of a storage hierarchy on a chip featuring different storage sizes and operation modes (read and write).

(Image Omitted)

Each operation mode is controlled by its own timing chain. The three timing chains are activated by RAS, CAS, and data gate DG. (RAS and CAS represent row address select and column address select, respectively.) The system designer can make a trade-off between memory size and performance, and can transfer data from the lower to the higher level with increasing speed. Multilevel storages on different chips are required no longer. The design offers the page mode and the buffer mode on the same chip. Another new feature is that during the page mode a buffer mode is possible.

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