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Wide Range Dynamic Differential Amplifier

IP.com Disclosure Number: IPCOM000042052D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Lo, TC: AUTHOR

Abstract

A differential amplifier is provided to amplify a small differential signal between input signal Vin and reference signal Vref and produce a pair of complementary high level output signals with a wide range of Vref values. The Wide Range Dynamic Differential Amplifier (WRDDA) shown in the figure consists of three parts: the steering circuit 1, the master flip-flop 3, and the slave flip-flop 5. The operation sequence is as follows: at quiescence, the reset clock øR is on, holding the output pair VO and VO at ground potential. Nodes 7 and 9 are precharged to an equal potential. The input node 11 and the reference node 13 are continually connected to the input terminal Vin and the reference terminal Vref, respectively.

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Wide Range Dynamic Differential Amplifier

A differential amplifier is provided to amplify a small differential signal between input signal Vin and reference signal Vref and produce a pair of complementary high level output signals with a wide range of Vref values. The Wide Range Dynamic Differential Amplifier (WRDDA) shown in the figure consists of three parts: the steering circuit 1, the master flip-flop 3, and the slave flip-flop 5. The operation sequence is as follows: at quiescence, the reset clock øR is on, holding the output pair VO and VO at ground potential. Nodes 7 and 9 are precharged to an equal potential. The input node 11 and the reference node 13 are continually connected to the input terminal Vin and the reference terminal Vref, respectively. Q9, Q10 and C3 form a filter to prevent charge robbing from the gate of Q1 which may occur when Vin goes negative due to noise after øR is turned off. A similar filter arrangement is provided on the Vref side. To activate the WRDDA, øR is first turned off, locking the differential signals at nodes 11 and
13. This is followed by the turn-on of the sense clock øS which boosts nodes 11 and 13 to higher workable levels through capacitors C1 and C2 . For Vref much greater than VT, capacitors C1 and C2 can be optionally deleted. The difference in the "on" resistance of Q1 and Q2 determines which way the master flip-flop sets. Accordingly, node 7 or node 9 is conditionally discharged by way of Q7 and Q8 to avoid DC c...