Browse Prior Art Database

TTL Input Buffer With Variable Input Levels

IP.com Disclosure Number: IPCOM000042060D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Doerre, GW: AUTHOR [+3]

Abstract

A new TTL (transistor-transistor logic) input buffer is shown which is capable of providing FET RAM chips with a variable reference voltage. A plurality of fuses are selectively opened to set the reference voltage through selected voltage dividers. The invention presents an improvement over conventional chip drive circuits which provide an invariable reference level. Fig. 1 shows a conventional TTL input buffer circuit used by the command inputs of FET RAM chips. The parallel-connected resistors R1 and R2 (R1 // R2) in hatched box 10 form a voltage divider which produces an invariable reference voltage Va (at Node A).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 71% of the total text.

Page 1 of 2

TTL Input Buffer With Variable Input Levels

A new TTL (transistor-transistor logic) input buffer is shown which is capable of providing FET RAM chips with a variable reference voltage. A plurality of fuses are selectively opened to set the reference voltage through selected voltage dividers. The invention presents an improvement over conventional chip drive circuits which provide an invariable reference level. Fig. 1 shows a conventional TTL input buffer circuit used by the command inputs of FET RAM chips. The parallel-connected resistors R1 and R2 (R1 // R2) in hatched box 10 form a voltage divider which produces an invariable reference voltage Va (at Node A). Resistors R1 and R2 are chosen so that Va=1/4(TTL LPUL - TTL MPDL), where "TTL LPUL" is the "lowest permissible up level" voltage (or the minimum voltage at which all the devices will turn on) and where "TTL MPDL" is the "maximum permissible down level" voltage (or the maximum voltage at which all the devices will turn off). See Fig. 1. The TTL logic T1-T4 will buffer the chip supply voltage CSA up from the TTL LPUL up voltage to a voltage of VH-VT. Since the reference voltage Va is invariable, the supplied voltage CSA will also be invariable. The circuit within hatched box 10 of Fig. 1 is replaced by the circuit in hatched box 100 of Fig. 2. The resistors are chosen such that R1A + R1B of Fig. 2 equal R1 of Fig. 1, and R2A + R2B of Fig. 2 equal R2 of Fig. 1. When fuse A in Fig. 2 is blown, transistor T5 t...