Browse Prior Art Database

Scaled FET ROM Programmed With Boron and Phosphorus Implantation

IP.com Disclosure Number: IPCOM000042061D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Adler, E: AUTHOR [+2]

Abstract

Implanting boron and phosphorus through the programming implant mask solves the reduction in breakdown voltage problem caused by implanting boron alone. Masked boron implantation through the gate electrode is a means often used to improve turn-around time in a polysilicon gate FET ROM product. This has the result of degrading the breakdown voltage between diffusion and substrate in the array cell to the point where the technique would not be usable for a gate oxide thinner than 450 ˜. The origin of the problem is that a large amount of boron must be used to implant the device for a threshold voltage of approximately 5 volts at 3 volts substrate bias. This implant must intersect the drain junction because isolation from the junction would require too much space in the array.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 70% of the total text.

Page 1 of 1

Scaled FET ROM Programmed With Boron and Phosphorus Implantation

Implanting boron and phosphorus through the programming implant mask solves the reduction in breakdown voltage problem caused by implanting boron alone. Masked boron implantation through the gate electrode is a means often used to improve turn-around time in a polysilicon gate FET ROM product. This has the result of degrading the breakdown voltage between diffusion and substrate in the array cell to the point where the technique would not be usable for a gate oxide thinner than 450 ~. The origin of the problem is that a large amount of boron must be used to implant the device for a threshold voltage of approximately 5 volts at 3 volts substrate bias. This implant must intersect the drain junction because isolation from the junction would require too much space in the array. A boron dose of 6x1012/cm2 is required to personalize a device with a 450 ~ gate to a VT of 5 volts. The resulting diffusion-to-substrate breakdown voltage, using an abrupt As junction, is about 10 volts. This is close to the toleration limit with nominal supplies, 5 volts VH, -3 volts VBB . Thinner oxides for higher performance and shorter channels would require higher boron doses to program, and could not be used with the above standard power supplies. A more graded junction could be used throughout the chip, such as produced by the combination of arsenic and phosphorus implants, but the junction is deeper and produces a large...