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Bootstrap Array Cell

IP.com Disclosure Number: IPCOM000042067D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Lewis, SC: AUTHOR

Abstract

The bootstrap array cell described below allows a 10-volt differential between a "1" and a "0" to be stored in a 5-volt design which also eliminates dummy half cells. The bootstrap array cell appears very similar to several others in structure. The exact structure and operation, however, provide several unique advantages. The cell is operated so that in standby the plate and the bit line are at 5 volts and the word line is at ground. The source node A in Fig. 1 is either at 0 volts or at +10 volts with respect to ground. The voltage across the storage capacitor, therefore, is either +5 volts or -5 volts. As in most 5-volt designs the word line is bootstrapped to about 1.6 x VH (approximately 8 volts). Thus, the bit line is either discharged by a "0" or charged by a "1".

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Bootstrap Array Cell

The bootstrap array cell described below allows a 10-volt differential between a "1" and a "0" to be stored in a 5-volt design which also eliminates dummy half cells. The bootstrap array cell appears very similar to several others in structure. The exact structure and operation, however, provide several unique advantages. The cell is operated so that in standby the plate and the bit line are at 5 volts and the word line is at ground. The source node A in Fig. 1 is either at 0 volts or at +10 volts with respect to ground. The voltage across the storage capacitor, therefore, is either +5 volts or -5 volts. As in most 5-volt designs the word line is bootstrapped to about 1.6 x VH (approximately 8 volts). Thus, the bit line is either discharged by a "0" or charged by a "1". The advantages in increased signal, tracking, and no dummy cell are similar to the twin cell without needing twice the area of a standard single-device cell. As shown in Fig. 2, the word line is bootstrapped as quickly as possible. In a read "1" the bit line begins charging positive only after the word line exceeds VH + Vt (i.e., VH + one threshold). The sense amp is then set. Since this operation is conventional, typical high performance access is possible. The bootstrapping that follows will, however, cause a cycle time increase. As soon as the sense amp is set, the plate "n" is pulled to ground while data is being transferred and latched in the I/O's. The word line is then...