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Patch Microcode Change Level Check

IP.com Disclosure Number: IPCOM000042079D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Weiss, L: AUTHOR

Abstract

This method ensures engineering change level compatibility between patch microcode located in random-access memory (RAM) and primary microcode located in read-only storage (ROS). This eliminates the unpredictable results that may occur when executing a microcode patch for one engineering change level in connection with the ROS microcode for another and different engineering change level. Microcode changes ("patches") are provided for ROS microcode by providing patch "hooks" in the ROS microcode which branch to appropriate locations in a RAM storage module. This enables blocks of ROS microcode to be bypassed and replaced by microcode patches located in the RAM module. If no patch code is present in the RAM, then the RAM code immediately branches back to the next sequential instruction in the ROS module.

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Patch Microcode Change Level Check

This method ensures engineering change level compatibility between patch microcode located in random-access memory (RAM) and primary microcode located in read-only storage (ROS). This eliminates the unpredictable results that may occur when executing a microcode patch for one engineering change level in connection with the ROS microcode for another and different engineering change level. Microcode changes ("patches") are provided for ROS microcode by providing patch "hooks" in the ROS microcode which branch to appropriate locations in a RAM storage module. This enables blocks of ROS microcode to be bypassed and replaced by microcode patches located in the RAM module. If no patch code is present in the RAM, then the RAM code immediately branches back to the next sequential instruction in the ROS module. In other words, the ROS-located "hooks" are activated by writing a desired patch microcode routine into the RAM storage at the address branched to by the ROS hook. At the end of the patch, the RAM code branches back to a specified location in the ROS storage. A problem occurs when a microcode patch at one engineering change level is inadvertently applied to a machine having ROS storage modules at an engineering change level other than the one the patch was intended for. This comes about when the customer software automatically loads existing microcode patches into the RAM storage during the initial program load of the RAM storage and such existing patches have not been modified or deleted to correspond to updated ROS modules which have been installed in the machine. To prevent executing a microcode patch when it does not apply as a part of the patch code for the installed ROS modules, an automatic engineering change level check is made as a preliminary step for each microcode patch to automatically determine if the patch change level matches the ROS module change level. If they match, the patch microcode is executed. If they do not match, th...