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Sense Latch Triggering Circuit

IP.com Disclosure Number: IPCOM000042090D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Cordaro, W: AUTHOR [+3]

Abstract

A particular known memory cell utilizes the poly word line and folded metal bit line to minimize the differential noise to the sense amplifier. Using a known constant delay technique, an absolute worst case of delay must be added to assure a sufficient sensing signal. A new technique is used in order to speed up the access time. This is accomplished by having a sense latch triggering circuit that tracks the process and supply voltage, thus assuring an adequate signal to the sense amplifier. The known cell relies on variable triggering level techniques to assure a sufficient sensing signal and a faster access time sort. The present sense latch triggering circuit is designed to set the sense latch at the earliest possible time. It consists of a Sample Word Line (SWL), shown in Fig.

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Sense Latch Triggering Circuit

A particular known memory cell utilizes the poly word line and folded metal bit line to minimize the differential noise to the sense amplifier. Using a known constant delay technique, an absolute worst case of delay must be added to assure a sufficient sensing signal. A new technique is used in order to speed up the access time. This is accomplished by having a sense latch triggering circuit that tracks the process and supply voltage, thus assuring an adequate signal to the sense amplifier. The known cell relies on variable triggering level techniques to assure a sufficient sensing signal and a faster access time sort. The present sense latch triggering circuit is designed to set the sense latch at the earliest possible time. It consists of a Sample Word Line (SWL), shown in Fig. 1, and a high input threshold clock driver (Fig. 2). The Sample Word Line is constructed just like a regular word line, except that all the storage nodes of transistors T101- T228 are tied together to a pull-down device, transistor T229. The purpose of the Sample Word Line is to simulate the worst-case word line rise time which occurs when all the storage nodes are storing a '0' (0 volts). The threshold voltage of the clock driver is designed such that it will track with the supply voltage (VDD) to prevent premature triggering at higher supply voltages. The clock driver threshold voltage can be adjusted by changing the size of the bootstrap capacitor CIN. T...