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Ttl-Compatible Tristate Fet Driver

IP.com Disclosure Number: IPCOM000042096D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Cheung, SK: AUTHOR [+4]

Abstract

A driver which has a tristate output and is compatible with TTL (transistor-transistor logic) is seen in the schematic diagram of Fig. 2. The driver achieves TTL-level compatibility by using a single 8.5-volt Å10% power supply, not requiring an additional 5-volt supply. Included is a unique feedback biasing circuit that allows initial bootstrapping action for speed and for achieving final level control so as to assure the desired TTL-level compatibility. The operation of the driver will be understood by reference to the timing diagram of Fig. 1. Transistor devices T1 and T2 are the data switch devices at the input of the circuit. Nodes 1 and 2 are initially precharged to a suitable level through transistors T5 and T6.

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Ttl-Compatible Tristate Fet Driver

A driver which has a tristate output and is compatible with TTL (transistor- transistor logic) is seen in the schematic diagram of Fig. 2. The driver achieves TTL-level compatibility by using a single 8.5-volt Å10% power supply, not requiring an additional 5-volt supply. Included is a unique feedback biasing circuit that allows initial bootstrapping action for speed and for achieving final level control so as to assure the desired TTL-level compatibility. The operation of the driver will be understood by reference to the timing diagram of Fig. 1. Transistor devices T1 and T2 are the data switch devices at the input of the circuit. Nodes 1 and 2 are initially precharged to a suitable level through transistors T5 and T6. The combination of transistors T3 and T4 and the combination of transistors T18- T30 are used for control purposes. In particular, transistors T21 through T24 constitute a latch circuit which provides the functions of either isolating the driver from an incoming signal or clamping down the nodes 1 and 2 to a low level. Transistors T25-T30 are arranged such that the driver is enabled only during the READ cycle (RWI signal) and when selected by the DG (data gate) signal. At all other times, the output is in a tristate region because transistors T15 and T17 are OFF. When the driver is not selected (i.e., DG is low), or during a WRITE cycle, internal nodes 1 and 2 are isolated from input data lines (IIO and IIO) and are discharged through transistors T3 and T4. Node 7, which is at the output of transistor T18, is clamped at a low level by that transistor; therefore, transistor T15 is OFF (transistor T17 is also OFF since node B is kept at a low level by transistor T20). During the normal operating mode, which is the READ cycle for a selected driver, the signal DG is high so that input data appear at the nodes 1 and 2. When signal AEC goes UP, node A is designed to be bootstrapped up to a higher level than VDD so that transistor T12 has little effect on the voltage- dividing network composed of transistors T11-T14. This voltage-dividing n...