Browse Prior Art Database

Address Translation for IBM Series/1 Channel Attachment to Bus Architected System

IP.com Disclosure Number: IPCOM000042106D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Bourke, DG: AUTHOR [+4]

Abstract

The eight I/O address spaces of 64 KB (512 KB) for the IBM Series/1 processor are expanded to the full 64 MB address range of the I/O in a bus architected (BA) system. Input/Output (I/O) attachment for the IBM Series/1 processor have a maximum addressing capability of eight 64 KB spaces. The Series/1 cycle steal attachments perform, for the most part, two-byte (Series/1 word aligned) data transfers for each cycle steal sequence. They address the Series/1 storage using a three-bit address key and 16 storage address lines. These device attachments provide no address translation and address the Series/1 storage with real addresses or logical addresses when the Series/1 Translator is installed.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Address Translation for IBM Series/1 Channel Attachment to Bus Architected System

The eight I/O address spaces of 64 KB (512 KB) for the IBM Series/1 processor are expanded to the full 64 MB address range of the I/O in a bus architected (BA) system. Input/Output (I/O) attachment for the IBM Series/1 processor have a maximum addressing capability of eight 64 KB spaces. The Series/1 cycle steal attachments perform, for the most part, two-byte (Series/1 word aligned) data transfers for each cycle steal sequence. They address the Series/1 storage using a three-bit address key and 16 storage address lines. These device attachments provide no address translation and address the Series/1 storage with real addresses or logical addresses when the Series/1 Translator is installed. A bus architected system, on the other hand, may support physical storage up to 64 MB and the native I/O Channels may be capable of addressing the full architected limits of physical storage. By adding a translation table array to the Series/1 Channel Attachment to the Bus System and issuing logical addresses to the Series/1 I/O attachments, they may obtain addressability to the full 64 MB range of the bus architected system. The figure depicts the address translation mechanism that provides this function. Prior to issuing a cycle steal command (Start I/O) to a Series/1 device, the BA/Series-1 device handler must set the translation table entry, in the Series/1 Channel Attachment, that corresponds with the Series/1 address key and the four high-order bits of the logical cycle steal address. This entry is set equal to the fourteen high-order BA address bits. When the Series/1 device attachment request...