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Mechanism to Support Bidirectional Data Transfer Operations Using a Single Line Buffer

IP.com Disclosure Number: IPCOM000042107D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 4 page(s) / 54K

Publishing Venue

IBM

Related People

Bourke, DG: AUTHOR [+4]

Abstract

Bidirectional Data Transfer Some device attachments of the IBM Series/1 processor read and write data under control from a single bidirectional Device Control Block (DCB). A DCB may direct a device to read data from storage and write data to storage from or to locations specified, sometimes implicitly, by addresses within the DCB. Support is provided here to those devices when attached to a bus architected system via the Series/1 Channel Attachment. The device handler for a bus architected (BA)/Series/1 configuration may have to construct DCBs that read from and write into the same real line of storage. This presents a problem to the line buffer mechanism in the Series/1 Channel Attachment (S/1-CA) to BA System Bus. The figure depicts the S/1-CA translation and line buffer mechanisms.

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Mechanism to Support Bidirectional Data Transfer Operations Using a Single Line Buffer

Bidirectional Data Transfer Some device attachments of the IBM Series/1 processor read and write data under control from a single bidirectional Device Control Block (DCB). A DCB may direct a device to read data from storage and write data to storage from or to locations specified, sometimes implicitly, by addresses within the DCB. Support is provided here to those devices when attached to a bus architected system via the Series/1 Channel Attachment. The device handler for a bus architected (BA)/Series/1 configuration may have to construct DCBs that read from and write into the same real line of storage. This presents a problem to the line buffer mechanism in the Series/1 Channel Attachment (S/1-CA) to BA System Bus. The figure depicts the S/1-CA translation and line buffer mechanisms. The translation table is used to translate the Series/1 device's logical address to the BA System Bus real address. It also contains information that helps to control the corresponding line buffer. The translation table entry (TTE) has been expanded to include a Read (R) bit and a Write (W) bit. These bits indicate the type of access or accesses that have occurred with respect to the corresponding Last Line Address (LLA) and associated line buffer. Actually, the Buffer Empty (BE) bit could be removed and the buffer empty condition could be indicated by both R-bit and W-bit being inactive. In any event, all three conditions have to be indicated. When a Series/1 device requests a read from storage and the associated line buffer is empty, a full line of data is read from storage, the R-bit in the corresponding TTE is set active and the addressed byte or half-word is gated onto the Series/1 data bus. Subsequent reads may occur without System Bus cycles until the Last Line Address (LLA) is crossed or the direction of transfer changes. If the direction of transfer changes from read to write, the S/1-CA detects this by comparing the Series/1 Input Indicator's state against the TTE Read Bit and Write Bit. The Series/1 write data is written into the line buffer, and the W-bit in the associated TTE is set active. When an access to the line buffer occurs and the LLA is crossed, the W-bit is examined and, if active, the line is written back to storage before the new line is accessed. If the direction of transfer changes from write to read, the line must be written to storage and then read back to the line buffer. The W-bit is set inactive, the R-bit is set active, and the addressed byte or half- word is gated to the Series/1 data bus. Allocation and deallocation of TTEs and purging of partially full line buffers at device-end time are a software function. Line Buffers By adding the data line buffers to the Series/1 Channel Attachment, a reduction of System Bus contention and an increase of Series/1 device data throughput in a bus architected (BA) system are realized. Since Ser...