Browse Prior Art Database

On-Chip Fault Realignment for Reliability and Yield Enhancement

IP.com Disclosure Number: IPCOM000042109D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Ryan, PM: AUTHOR

Abstract

On-chip permutation logic provides a very powerful method of reconfiguring (and thus repairing) memories containing faulty components. A fault-tolerant memory chip array is described having permutation logic on each chip for permuting "island" portions of each chip to different addressed logical chip rows in order to place no more than one bit from one faulty "island" into the same accessed ECC word. The use of a large number of small permutable memory units (islands) - rather than the smaller number of larger permutable memory units (chips) of some prior fault-tolerant array disclosures - permits the use of initially untested faulty memory chips and achieves faster fault realignment. Consider a memory organized as shown in Fig. 1.

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On-Chip Fault Realignment for Reliability and Yield Enhancement

On-chip permutation logic provides a very powerful method of reconfiguring (and thus repairing) memories containing faulty components. A fault-tolerant memory chip array is described having permutation logic on each chip for permuting "island" portions of each chip to different addressed logical chip rows in order to place no more than one bit from one faulty "island" into the same accessed ECC word. The use of a large number of small permutable memory units (islands) - rather than the smaller number of larger permutable memory units (chips) of some prior fault-tolerant array disclosures - permits the use of initially untested faulty memory chips and achieves faster fault realignment. Consider a memory organized as shown in Fig. 1. When an address is presented, part of it selects one row of chips and the rest of it selects a particular cell on each of the selected chips. K, the number of chip columns, is usually equal to the number of bits in an ECC word; typical values are 22, 39, 40, 72, but other values are possible. N, the number of chip rows, is typically a binary multiple of the form 2m, where m is an integer; N is typically given a value in the range of 2 to 64. The memory (BSM) may be built on one or several cards. For simplicity in what follows, it is assumed that the memory chips each provide single-bit I/O per address; chips with multiple-bit I/O can be handled similarly. The chips used to build the memory each contain R rows of C columns each of cells, where both R and C are usually binary multiples, i.e., 2 raised to an integer power. Typically, R and C are 128, 256, or 512. This is shown in Fig. 2. To achieve the improvement, each chip is divided into logical islands, as outlined in Fig. 3. Each chip is provided with a small amount of additional storage to contain the chip-row personality of each island. There are L such islands per chip, each carrying an (m+1) bit chip-row personality. The "extra" bit may be used to define an address space larger than what is physically supported by the 2m chip rows, which allows some flexibility i...