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Three-Device Nonvolatile RAM Cell

IP.com Disclosure Number: IPCOM000042112D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Cassidy, BM: AUTHOR [+4]

Abstract

A nonvolatile RAM cell is disclosed which is not required to refresh data during the transition from the volatile state to the nonvolatile state. A four-port cell circuit is shown in the figure which includes a floating gate for the transistor T1, which is capacitively coupled to the capacitor C1. To electrically store data in a nonvolatile manner, electrons are injected into the floating gate of the transistor T1 to thereby increase the threshold voltage of the four-port device. To restore the device, the excess electrons are removed from the floating gate. The figure shows a low-voltage electrically erasable programmable read-only memory FET device 12 which includes the transistor T1, the switched resistance capacitor C2 and the capacitor C1.

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Three-Device Nonvolatile RAM Cell

A nonvolatile RAM cell is disclosed which is not required to refresh data during the transition from the volatile state to the nonvolatile state. A four-port cell circuit is shown in the figure which includes a floating gate for the transistor T1, which is capacitively coupled to the capacitor C1. To electrically store data in a nonvolatile manner, electrons are injected into the floating gate of the transistor T1 to thereby increase the threshold voltage of the four-port device. To restore the device, the excess electrons are removed from the floating gate. The figure shows a low-voltage electrically erasable programmable read-only memory FET device 12 which includes the transistor T1, the switched resistance capacitor C2 and the capacitor C1. The FET device T1 has its source/drain path connected between a first node N1 and a second node N2, and it has its gate node N3 connected through the first capacitor C1 to the control line CL. The gate node N3 is also connected through the second, switched resistance capacitor C2 to a fourth node N4. A second FET write transfer device T2 has its source/drain path connected between a bit line BL and the second node N2 and its gate connected to a write word line WL. A third FET device T3 has its source/drain path connected between the node N4 and ground potential, and its gate connected to the first node N1. The write transfer FET device T2 selectively supplies charge to the first node N1 through the first FET device T1, when the write word line WL is switched on while a first FET device...