Browse Prior Art Database

Two-Write, Multi-Read RAM Cell

IP.com Disclosure Number: IPCOM000042114D
Original Publication Date: 1984-Mar-01
Included in the Prior Art Database: 2005-Feb-03
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Ritchie, LC: AUTHOR [+2]

Abstract

A RAM (random-access memory) cell having two write lines and multiple read lines is disclosed. Fig. 1 shows a single-port RAM cell for a chip containing logic and memory elements. W is the write line to control the write operation. When W is at up level, it allows the information at the data-in (DI) node, either at up or down level, to flip the RAM cell to a given state. R is the read line which controls the read operation. When R is up, it allows the sense transistor T5 to sense the voltage level at the C2 node. SA is the sense amplifier node. Fig. 2 shows a two-write, multi-read RAM cell. W1 and W2 are two separate write control lines. The system logic will be set to prevent the simultaneous writing into the same cell at the same time.

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Two-Write, Multi-Read RAM Cell

A RAM (random-access memory) cell having two write lines and multiple read lines is disclosed. Fig. 1 shows a single-port RAM cell for a chip containing logic and memory elements. W is the write line to control the write operation. When W is at up level, it allows the information at the data-in (DI) node, either at up or down level, to flip the RAM cell to a given state. R is the read line which controls the read operation. When R is up, it allows the sense transistor T5 to sense the voltage level at the C2 node. SA is the sense amplifier node. Fig. 2 shows a two- write, multi-read RAM cell. W1 and W2 are two separate write control lines. The system logic will be set to prevent the simultaneous writing into the same cell at the same time. This means that W1 and W2, when connected to the same cell, are not allowed to go up at the same moment. It is noted that the information (up or down level) seen at node DI1 is just the opposite to that set at node DI2 in order to produce a consistent state stored by the RAM cell. R' and R" are two of the many read control lines which allow the voltage level at node C2 to be sensed by sense amplifiers SA1, SA2... .

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