# High Density Emitter Coupled Logic

Original Publication Date: 1984-Mar-01

Included in the Prior Art Database: 2005-Feb-03

## Publishing Venue

IBM

## Related People

## Abstract

Conventional cascode circuits shown in Fig. 1, in which the current is switched to successively higher cascode emitter coupled transistor pairs, use a lot of the chip area for wiring. The reason is that each transistor pair in the cascode requires a differential logic signal at the bases to switch the current. So for each transistor pair, two wires must be routed from the driving circuit. Each variable in a logic expression requires a transistor pair. For example, the expression A OR B requires two transistor pairs; one pair of the A variable and one pair for B. This requires input wires ÅA and ÅB (Fig. 1). The truth table in Fig. 1A shows that only if A and B are both up will the current flow into the left load resistor. Otherwise, current flows in the right load resistor which represents A OR B. As shown in Fig.

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__Page 1 of 3__**High Density Emitter Coupled Logic **

Conventional cascode circuits shown in Fig. 1, in which the current is switched
to successively higher cascode emitter coupled transistor pairs, use a lot of the
chip area for wiring. The reason is that each transistor pair in the cascode
requires a differential logic signal at the bases to switch the current. So for each
transistor pair, two wires must be routed from the driving circuit. Each variable in
a logic expression requires a transistor pair. For example, the expression A OR
B requires two transistor pairs; one pair of the A variable and one pair for B. This
requires input wires ÅA and ÅB (Fig. 1). The truth table in Fig. 1A shows that
only if A and B are both up will the current flow into the left load resistor.
Otherwise, current flows in the right load resistor which represents A OR B. As
shown in Fig. 2, this same logic function, the AND (or OR) of two variables, can
be implemented with only two transistors 10, 11. The signals representing the
two logic variables are applied to the two bases 10B, 11B. Which logic function
to perform is dictated by the voltage levels associated with the logic signals.
Since A's up level is higher than B's up level, if A is up, then current will flow in
the right transistor regardless of whether B is up or down. On the other hand, if A
is low (4.6 volts), then B will decide where the current is steered. If B is at 4.8
volts, then B is higher than A and current is steered left. If B is at 4.4 volts, then
the current is steered right. Thus, only if A is down AND B is up will current flow
in the left load resistor. Conversely, if A is up OR if B is down, current will flow in
the right load resistor. Thus, the same logic function can be performed with only
two transistors and two signal wires rather than four transistors and four wires.
This technique is not limited to two-variable logic but can be applied to many-
variable combination logic by combining transistor pairs, as shown in Figs. 3 and

4. The same logic function (A OR B OR C OR D) and (E OR F OR G OR H) is
implemented in the conventional implementation in Fig. 3, requiring 16 transistors
and 16 global wires for input signals. The Fig. 4 implementation requires eight
transistors and eight global wires. A factor of two savings in wires and devices
applies when the number of logic variables is even. When an odd number of
variables is required, one more device and wire must be added. As an example,
in Fig. 4, if the logic expression has no H ter...